Hi, habe folgenden Code mit VHDL-2008 in Modelsim kompiliert und simuliert. Wider meiner Erwartung ist der Ausgangsport Q undefiniert. Kann mir jemand sagen, wieso Q nicht die Werte von vec widerspiegelt? Grüße, DuArte
1 | library ieee; |
2 | use ieee.std_logic_1164.all; |
3 | use ieee.numeric_std.all; |
4 | |
5 | |
6 | entity test_shared is |
7 | port( Q : out std_logic_vector(3 downto 0) ); |
8 | end test_shared; |
9 | |
10 | |
11 | architecture xyz of test_shared is |
12 | |
13 | signal clock : std_logic; |
14 | signal cnt : unsigned(1 downto 0) := "00"; |
15 | shared variable vec : std_logic_vector(3 downto 0); |
16 | |
17 | begin
|
18 | |
19 | Q <= vec; |
20 | |
21 | Clk: process |
22 | begin
|
23 | clock <= '1'; wait for 10 ns; |
24 | clock <= '0'; wait for 10 ns; |
25 | end process; |
26 | |
27 | |
28 | Count: block |
29 | begin
|
30 | cnt <= cnt + 1 when rising_edge(clock); |
31 | end block; |
32 | |
33 | |
34 | Share1: process |
35 | begin
|
36 | wait until clock='1'; |
37 | |
38 | if cnt="00" then |
39 | vec := "ZZZZ"; |
40 | end if; |
41 | end process; |
42 | |
43 | |
44 | |
45 | Share2: process |
46 | begin
|
47 | wait until clock='1'; |
48 | |
49 | if cnt/="00" then |
50 | vec := "1111"; |
51 | end if; |
52 | end process; |
53 | |
54 | |
55 | |
56 | end xyz; |