1 | // perform system reset
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2 |
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3 | enc28j60WriteOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
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4 | // check CLKRDY bit to see if reset is complete
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5 | delay(50);
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6 | while(!(enc28j60Read(ESTAT) & ESTAT_CLKRDY));
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7 | // do bank 0 stuff
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8 | // initialize receive buffer
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9 | // 16-bit transfers, must write low byte first
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10 | // set receive buffer start address
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11 | NextPacketPtr = RXSTART_INIT;
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12 | enc28j60Write(ERXSTL, RXSTART_INIT&0xFF);
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13 | enc28j60Write(ERXSTH, RXSTART_INIT>>8);
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14 | // set receive pointer address
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15 | enc28j60Write(ERXRDPTL, RXSTART_INIT&0xFF);
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16 | enc28j60Write(ERXRDPTH, RXSTART_INIT>>8);
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17 | // set receive buffer end
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18 | // ERXND defaults to 0x1FFF (end of ram)
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19 | enc28j60Write(ERXNDL, RXSTOP_INIT&0xFF);
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20 | enc28j60Write(ERXNDH, RXSTOP_INIT>>8);
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21 | // set transmit buffer start
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22 | // ETXST defaults to 0x0000 (beginnging of ram)
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23 | //uart_puts("- enc28j60init - Schreibe erstes nibble - 03\n");
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24 | enc28j60Write(ETXSTL, TXSTART_INIT&0xFF);
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25 | //uart_puts("- enc28j60init - Schreibe zweites nibble - 03\n");
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26 | enc28j60Write(ETXSTH, TXSTART_INIT>>8);
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27 | // do bank 2 stuff
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28 | // enable MAC receive
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29 | enc28j60Write(MACON1, MACON1_MARXEN|MACON1_TXPAUS|MACON1_RXPAUS);
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30 | // bring MAC out of reset
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31 | enc28j60Write(MACON2, 0x00);
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32 | // enable automatic padding and CRC operations
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33 | enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);
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34 | // set inter-frame gap (non-back-to-back)
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35 | enc28j60Write(MAIPGL, 0x12);
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36 | enc28j60Write(MAIPGH, 0x0C);
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37 | // set inter-frame gap (back-to-back)
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38 | enc28j60Write(MABBIPG, 0x12);
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39 | // Set the maximum packet size which the controller will accept
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40 | enc28j60Write(MAMXFLL, MAX_FRAMELEN&0xFF);
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41 | enc28j60Write(MAMXFLH, MAX_FRAMELEN>>8);
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42 | // do bank 3 stuff
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43 | // write MAC address
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44 | // NOTE: MAC address in ENC28J60 is byte-backward
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45 | enc28j60Write(MAADR5, ENC28J60_MAC0);
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46 | enc28j60Write(MAADR4, ENC28J60_MAC1);
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47 | enc28j60Write(MAADR3, ENC28J60_MAC2);
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48 | enc28j60Write(MAADR2, ENC28J60_MAC3);
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49 | enc28j60Write(MAADR1, ENC28J60_MAC4);
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50 | enc28j60Write(MAADR0, ENC28J60_MAC5);
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51 | // no loopback of transmitted frames
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52 | enc28j60PhyWrite(PHCON2, PHCON2_HDLDIS);
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53 | // switch to bank 0
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54 | enc28j60SetBank(ECON1);
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55 | // enable interrutps
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56 | enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE|EIE_PKTIE);
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57 | // enable packet reception
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58 | enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
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