VHDL Fehler---WO?

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY huedic IS
PORT(  A    :IN STD_LOGIC;
    B    :IN STD_LOGIC;
    C    :IN STD_LOGIC;
    D    :IN STD_LOGIC;
    S0    :IN STD_LOGIC;
    S1    :IN STD_LOGIC;
    Lock  :IN STD_LOGIC;

    W    :OUT STD_LOGIC;
    X    :OUT STD_LOGIC;
    Y    :OUT STD_LOGIC;
    Z    :OUT STD_LOGIC);

END huedic;

ARCHITECTURE logic OF huedic IS
 SIGNAL Sx    :STD_LOGIC;
 SIGNAL SLock  :STD_LOGIC;

BEGIN


    W  <= (Sx AND not S0 AND not S1 AND SLock);
    X  <= (Sx AND not S0 AND S1 AND SLock);
    Y  <= (Sx AND S0 AND not S1 AND SLock );
    Z  <= (Sx AND S0 AND S1 AND SLock );
//Diese Zeile//  Sx <= (A AND not S0 AND not S1 AND SLock) OR (B AND not 
SO AND S1 AND SLock) OR (C AND S0 AND not S1 AND SLock) OR (D AND S0 AND 
S1 AND SLock);
    SLock <= Lock;

END logic;





Ich bekomme 7 mal den gleichen Fehler in der Zeile wo ich Sx zuweise. 
Der Fehler heißt "Subprogram error: can't interpret subprogram call" Wo 
liegt der fehler?

Das Programm soll nicht viel machen. Sx ist der Ausgang eines 
Multiplexers und W-Z stellt die Ausgänge eines Dmux dar.

LG