Guten Tag,
Ich sitze im Moment an einem Problem und weiß nicht wirklich woher es
kommt.
Also, was möchte ich beschreiben:
Einen Eingangsmultiplexer, welcher mit IN_MODE das interne Signal
auswählt und einen Ausgangsmultiplexer, welcher mittels OUT_MODE das
interne Signal auf verschiedene Ausgänge aufteilen kann.
Was wird draus:
Anstelle des Ausgangsmultiplexers werden zwei 8 bit lachtes erzeugt.
Hier mein Code:
1 | library IEEE;
|
2 | use IEEE.STD_LOGIC_1164.ALL;
|
3 |
|
4 | entity Instruction_Ex is
|
5 | Port ( CLK : in std_logic;
|
6 | INPUT_ALU : in std_logic_vector (7 downto 0);
|
7 | INPUT_BYP : in std_logic_vector(7 downto 0);
|
8 | INPUT_MODE : in std_logic_vector (1 downto 0);
|
9 | OUTPUT_MODE : in std_logic_vector (1 downto 0);
|
10 | OUTPUT_REG : out std_logic_vector (7 downto 0);
|
11 | OUTPUT_DIRECT : out std_logic_vector (7 downto 0));
|
12 | end Instruction_Ex;
|
13 |
|
14 | architecture Behavioral of Instruction_Ex is
|
15 |
|
16 | signal output_int : std_logic_vector(7 downto 0);
|
17 | signal input_int : std_logic_vector (7 downto 0);
|
18 |
|
19 | begin
|
20 |
|
21 | INPUTMux:process(INPUT_MODE,INPUT_ALU,INPUT_BYP)
|
22 | begin
|
23 | case INPUT_MODE is
|
24 | when "00" =>
|
25 | input_int <= INPUT_ALU;
|
26 | when "01" =>
|
27 | input_int <= INPUT_BYP;
|
28 | when others =>
|
29 | input_int <= INPUT_ALU;
|
30 | end case;
|
31 | end process;
|
32 |
|
33 | OUTPUTMux:process(OUTPUT_MODE,input_int,INPUT_ALU,INPUT_BYP,INPUT_MODE)
|
34 | begin
|
35 | case OUTPUT_MODE is
|
36 | when "00" =>
|
37 | OUTPUT_REG <= input_int;
|
38 | when "01" =>
|
39 | OUTPUT_DIRECT <= input_int;
|
40 | when others =>
|
41 | OUTPUT_REG <= input_int;
|
42 | end case;
|
43 | end process;
|
44 |
|
45 | end Behavioral;
|