Berechnungen in VHDL

[Boris (Gast)]

Hallo zusammen,
ich hoffe hier kann mir jemand ein paar Tips zu generics in VHDL geben. 
(Oder auch einen alternativen Lösungsweg für meine Aufgabe nennen.)
Und zwar habe ich folgendes Problem. Ich habe einen Core geschrieben, 
welcher an einem AXI hängt. Der Core hat zwei Generics. Ein mal den Wert 
des Clock-Takts und ein mal den der Sample-Rate. Mit diesen beiden Werte 
will ich mir mit Hilfe eines Zählers ein enable-Signal erzeugen um Daten 
von einem ADC entgegen zu nehmen. Derzeit hat die CLK eine Frequenz von 
50MHz und die Samplefrequenz ist 600 kSps. Leider schaffe es nicht dass 
die Synthese sich diese Werte selbst errechnet.
Meine Formel lautet:
f(x)=round(x*(CLK/Samplerate)-round(x*(CLK/Samplerate))+CLK/Samplerate
Hier mal ein Auszug aus meinem VHDL-Code und die zugehörige 
Fehlermeldung:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;

entity core_logic is
    generic(
      C_S_AXI_ACLK_FREQ_HZ : integer := 50_000_000;
      sample_rate : integer := 9_600_000
      );
    port(
      clk : in  STD_LOGIC;
...
architecture Behavioral of core_logic is

signal sample_en : integer range 0 to 15 := 0;
...
sample_en_process : process begin
   wait until rising_edge(clk);
   if sample_en = counter-1 then
      sample_en <= 0;
    sample_cnt <= sample_cnt +1;
   else
      if sample_rdy_i = '1' then
         sample_en <= 0;
      sample_cnt <= 0;
      else
         sample_en <= sample_en + 1;
      end if;
   end if;
end process;

counter_process : process begin
  wait until rising_edge(clk);
  case sample_cnt is
    when 0 =>  counter <= (ROUND((C_S_AXI_ACLK_FREQ_HZ/sample_rate)));--5;
    when 1 =>  counter <= (ROUND(1*(C_S_AXI_ACLK_FREQ_HZ/sample_rate)-ROUND(1*(C_S_AXI_ACLK_FREQ_HZ/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate)));
    when 2 =>  counter <= (ROUND(2*(C_S_AXI_ACLK_FREQ_HZ/sample_rate)-ROUND(2*(C_S_AXI_ACLK_FREQ_HZ/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate)));
    when 3 =>  counter <= (ROUND(3*(C_S_AXI_ACLK_FREQ_HZ/sample_rate)-ROUND(3*(C_S_AXI_ACLK_FREQ_HZ/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate)));
    when 4 =>  counter <= (ROUND(4*(C_S_AXI_ACLK_FREQ_HZ/sample_rate)-ROUND(4*(C_S_AXI_ACLK_FREQ_HZ/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate)));
    when 5 =>  counter <= (ROUND(5*(C_S_AXI_ACLK_FREQ_HZ/sample_rate)-ROUND(5*(C_S_AXI_ACLK_FREQ_HZ/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate)));
    when 6 =>  counter <= (ROUND(6*(C_S_AXI_ACLK_FREQ_HZ/sample_rate)-ROUND(6*(C_S_AXI_ACLK_FREQ_HZ/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate)));
    when 7 =>  counter <= (ROUND(7*(C_S_AXI_ACLK_FREQ_HZ/sample_rate)-ROUND(7*(C_S_AXI_ACLK_FREQ_HZ/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate)));
    when 8 =>  counter <= (ROUND(8*(C_S_AXI_ACLK_FREQ_HZ/sample_rate)-ROUND(8*(C_S_AXI_ACLK_FREQ_HZ/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate)));
    when 9 =>  counter <= (ROUND(9*(C_S_AXI_ACLK_FREQ_HZ/sample_rate)-ROUND(9*(C_S_AXI_ACLK_FREQ_HZ/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate)));
    when 10 => counter <= (ROUND(10*(C_S_AXI_ACLK_FREQ_HZ/sample_rate)-ROUND(10*(C_S_AXI_ACLK_FREQ_HZ/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate)));
    when 11 => counter <= (ROUND(11*(C_S_AXI_ACLK_FREQ_HZ/sample_rate)-ROUND(11*(C_S_AXI_ACLK_FREQ_HZ/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate)));
    when 12 => counter <= (ROUND(12*(C_S_AXI_ACLK_FREQ_HZ/sample_rate)-ROUND(12*(C_S_AXI_ACLK_FREQ_HZ/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate)));
    when 13 => counter <= (ROUND(13*(C_S_AXI_ACLK_FREQ_HZ/sample_rate)-ROUND(13*(C_S_AXI_ACLK_FREQ_HZ/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate)));
    when 14 => counter <= (ROUND(14*(C_S_AXI_ACLK_FREQ_HZ/sample_rate)-ROUND(14*(C_S_AXI_ACLK_FREQ_HZ/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate)));
    when 15 => counter <= (ROUND(15*(C_S_AXI_ACLK_FREQ_HZ/sample_rate)-ROUND(15*(C_S_AXI_ACLK_FREQ_HZ/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate)));
    when others => counter <= (ROUND(15*(C_S_AXI_ACLK_FREQ_HZ/sample_rate)-ROUND(15*(C_S_AXI_ACLK_FREQ_HZ/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate)));
  end case;
end process;
...
data_sampling_process : process begin
   wait until rising_edge(clk) and sample_en = 0;
   ch1_out_i <= ch1_out_i(14 downto 0) & channel1_i;
   ch2_out_i <= ch2_out_i(14 downto 0) & channel2_i;
end process;

[Boris (Gast)]

Boris schrieb:
> counter_process : process begin
>   wait until rising_edge(clk);
>   case sample_cnt is
>     when 0 =>  counter <= (ROUND((C_S_AXI_ACLK_FREQ_HZ/sample_rate)));--5;
>     when 1 =>  counter <= 
(ROUND(1*(C_S_AXI_ACLK_FREQ_HZ/sample_rate)-ROUND(1*(C_S_AXI_ACLK_FREQ_H 
Z/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate)));

Ich bin leider statt auf Vorschau auf senden bekommen und konnte so die 
letzte Änderung im VHDL nicht mehr einfügen.
Der zitierte Code-Schnippsel lautet derzeit so:

counter_process : process begin
  wait until rising_edge(clk); -- enable wird hier fehlen!!!
  case sample_cnt is
    when 0 =>  counter <= integer(ROUND((C_S_AXI_ACLK_FREQ_HZ/sample_rate)));
    when 1 =>  counter <= integer(ROUND(1*(C_S_AXI_ACLK_FREQ_HZ/sample_rate)-ROUND(1*(C_S_AXI_ACLK_FREQ_HZ/sample_rate))+(C_S_AXI_ACLK_FREQ_HZ/sample_rate)));

Und die Fehlermeldung sieht dann so aus:

ERROR:HDLCompiler:1731 - "/home/CORRAIL/metka/tmp/sensor_head_simulation/core_logic.vhd" Line 122: found '0' definitions of operator "/", cannot determine exact overloaded matching definition for "/"
ERROR:HDLCompiler:1731 - "/home/CORRAIL/metka/tmp/sensor_head_simulation/core_logic.vhd" Line 123: found '0' definitions of operator "*", cannot determine exact overloaded matching definition for "*"

Ich freue mich schon über euren Input.
Gruß Boris

[jjj (Gast)]

Hey Boris,

hoffe du liest das noch ...
Round erwartet einen floating Datentyp.... Du gibts ihm Integer/Integer= 
abgehackter Integer

Probier mal das ...

constant C_S_AXI_ACLK_FREQ_HZ : integer := 50_000_000;
constant sample_rate : integer := 9_600_000;
constant test : integer := integer((ROUND(real(C_S_AXI_ACLK_FREQ_HZ)/real(sample_rate))));