DCM einbinden? Error:Xst:2585

[Ramon F. (tronixx)]

Aus dem EINTRAG Beitrag "Spartan3 DCM geht nicht"


Hallo zusammen,

ich hänge an einem ähnlochen problem um mein DCM einzubinden.
Hab mir mit dem IP core ein DCM nach wünschen erzeugt

50 MHz rein  ->   50 und 18 Mhz raus.

die HDL Instantiation Template hab ich dann wie folgt in ein neues VHDL
Modul eingebunden und daraus ein Schematic Symbol erstellt und mit in
meine top level Schematic eingebunden. Simulation klappt auch
einwandfrei soweit. Nur bei der Synthese meckert er folgendes:
Was mach ich denn hier falsch. Suche im Netz hat mich nicht gerade
weitergebracht

------------------------------------------------------------------------
-
ERROR:Xst:2585 - Port <CLK0> of instance <DCM_INST> does not exist in
definition <DCM>. Please compare the definition of block <DCM> to its
component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <CLK180> of instance <DCM_INST> does not exist in
definition <DCM>. Please compare the definition of block <DCM> to its
component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <CLK270> of instance <DCM_INST> does not exist in
definition <DCM>. Please compare the definition of block <DCM> to its
component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <CLK2X> of instance <DCM_INST> does not exist in
definition <DCM>. Please compare the definition of block <DCM> to its
component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <CLK2X180> of instance <DCM_INST> does not exist
in definition <DCM>. Please compare the definition of block <DCM> to its
component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <CLK90> of instance <DCM_INST> does not exist in
definition <DCM>. Please compare the definition of block <DCM> to its
component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <CLKDV> of instance <DCM_INST> does not exist in
definition <DCM>. Please compare the definition of block <DCM> to its
component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <CLKFB> of instance <DCM_INST> does not exist in
definition <DCM>. Please compare the definition of block <DCM> to its
component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <CLKFX> of instance <DCM_INST> does not exist in
definition <DCM>. Please compare the definition of block <DCM> to its
component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <CLKFX180> of instance <DCM_INST> does not exist
in definition <DCM>. Please compare the definition of block <DCM> to its
component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <CLKIN> of instance <DCM_INST> does not exist in
definition <DCM>. Please compare the definition of block <DCM> to its
component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <DSSEN> of instance <DCM_INST> does not exist in
definition <DCM>. Please compare the definition of block <DCM> to its
component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <LOCKED> of instance <DCM_INST> does not exist in
definition <DCM>. Please compare the definition of block <DCM> to its
component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <PSCLK> of instance <DCM_INST> does not exist in
definition <DCM>. Please compare the definition of block <DCM> to its
component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <PSDONE> of instance <DCM_INST> does not exist in
definition <DCM>. Please compare the definition of block <DCM> to its
component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <PSEN> of instance <DCM_INST> does not exist in
definition <DCM>. Please compare the definition of block <DCM> to its
component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <PSINCDEC> of instance <DCM_INST> does not exist
in definition <DCM>. Please compare the definition of block <DCM> to its
component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <RST> of instance <DCM_INST> does not exist in
definition <DCM>. Please compare the definition of block <DCM> to its
component declaration to detect the mismatch.
ERROR:Xst:2585 - Port <STATUS> of instance <DCM_INST> does not exist in
definition <DCM>. Please compare the definition of block <DCM> to its
component declaration to detect the mismatch.
------------------------------------------------------------------------
-

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;

library UNISIM;
use UNISIM.Vcomponents.ALL;



entity DCM_x is
    Port ( clk_50 : in  STD_LOGIC;
           clk18 : out  STD_LOGIC;
        Reset         : in    std_logic; 
        CLK0        : out   std_logic); 

end DCM_x;

architecture Behavioral of DCM_x is

COMPONENT DCM_test
  PORT(
    CLKIN_IN : IN std_logic;
    RST_IN : IN std_logic;          
    CLKFX_OUT : OUT std_logic;
    CLKIN_IBUFG_OUT : OUT std_logic;
    CLK0_OUT : OUT std_logic;
    LOCKED_OUT : OUT std_logic
    );
  END COMPONENT;
  
begin

Inst_DCM_test: DCM_test PORT MAP(
    CLKIN_IN => clk_50,
    RST_IN => Reset,
    CLKFX_OUT => clk18,
    CLKIN_IBUFG_OUT => open ,
    CLK0_OUT => CLK0 ,
    LOCKED_OUT => open 
  );


end Behavioral;

Lothar Miller schriebt:
>Du gibst die Zielarchitektur und die ISE-Version nicht an!

Das musst du mir jetz bitte etwas genauer erklären. Wo muss ich die denn 
angeben?

[Lothar M. (Firma: Titel) (lkmiller) (Moderator)]

Ramon F. schrieb:
> Das musst du mir jetz bitte etwas genauer erklären. Wo muss ich die denn
> angeben?
Hier. Kann ja sein, dass du einen Artix verwendest, der einen ganz 
anderen DCM hat als der Spartan 3. Und dass deshalb die Ports nicht 
passen...

[Ramon F. (tronixx)]

>Hier. Kann ja sein, dass du einen Artix verwendest, der einen ganz
>anderen DCM hat als der Spartan 3. Und dass deshalb die Ports nicht
>passen...

also gemäß Abb. 1-2 hab ich das ganze erstellt!

nach dem Erstellen hab ich einfach ein neues VHDL_modul : DCM_x 
erstellt und die Komponente DCM_test eingebunden.
Anschließend vom DCM_x ein Symbol erstellt und in meiner Main.sch 
eingefügt. Simulation passt einwandfrei. Nur bei der Synthese meckert 
er.
Hab vorher noch nie mit dem IP Core gearbeitet bzw ihn mit eingebunden. 
hab ich iwas noch vergessen ? Gibts noch ne andere Möglichkeit?

Angaben zu Board:  Spartan 3 s200 von Digilent!

MfG

[Lothar M. (Firma: Titel) (lkmiller) (Moderator)]

Ramon F. schrieb:
> Hab vorher noch nie mit dem IP Core gearbeitet bzw ihn mit eingebunden.
Mein Beispiel hat auch gar nichts mit einem Core zu tun. Ich habe 
einfach die Komponente DCM manuell instatiiert. So etwa wie im 
Beitrag "Re: Spartan3 DCM geht nicht"
Hier gibts auch was zum Thema:
http://forums.xilinx.com/t5/Archived-ISE-issues/Instantiating-DCM-using-Language-Templates-in-ISE-9-2i/td-p/16807


BTW:
Ramon F. schrieb:
> Aus dem EINTRAG [ [Spartan3 DCM geht nicht]]
Mit eckigen Klammern wird auf einen Artikel verwiesen. Einen Link auf 
einen anderen Thread bekommst du einfach durch das Herkopieren der URL 
aus dem Browser:
https: //www.mikrocontroller.net/topic/196719#1927578
--> ohne Leerzeichen:
Beitrag "Re: Spartan3 DCM geht nicht"

[Ramon F. (tronixx)]

Hallo,

also erst ma vielen Danke Lothar für deine kommis.
Hab mir jetz ohne den core folgendes DCM erstellt:
läuft einwandfrei, synthese klappt, Simulation klappt.
Und nun, es wär ja auch zu schön um wahr zu sein meckert die 
Implementierung beim Translate. Ich dreh hier gl echt durch. Was hab ich 
denn nun vergessen?

ERROR:NgdBuild:604 - logical block 'XLXI_7/DCM_SP_inst' with type 'DCM_SP' could
   not be resolved. A pin name misspelling can cause this, a missing edif or ngc
   file, case mismatch between the block name and the edif or ngc file name, or
   the misspelling of a type name. Symbol 'DCM_SP' is not supported in target
   'spartan3'.

+

WARNING:NgdBuild:486 - Attribute "CLKDV_DIVIDE" is not allowed on symbol
   "XLXI_7/DCM_SP_inst" of type "DCM_SP".  This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "CLKFX_DIVIDE" is not allowed on symbol
   "XLXI_7/DCM_SP_inst" of type "DCM_SP".  This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "CLKFX_MULTIPLY" is not allowed on symbol
   "XLXI_7/DCM_SP_inst" of type "DCM_SP".  This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "CLKIN_DIVIDE_BY_2" is not allowed on symbol
   "XLXI_7/DCM_SP_inst" of type "DCM_SP".  This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "CLKIN_PERIOD" is not allowed on symbol
   "XLXI_7/DCM_SP_inst" of type "DCM_SP".  This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "CLKOUT_PHASE_SHIFT" is not allowed on symbol
   "XLXI_7/DCM_SP_inst" of type "DCM_SP".  This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "CLK_FEEDBACK" is not allowed on symbol
   "XLXI_7/DCM_SP_inst" of type "DCM_SP".  This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "DESKEW_ADJUST" is not allowed on symbol
   "XLXI_7/DCM_SP_inst" of type "DCM_SP".  This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "DFS_FREQUENCY_MODE" is not allowed on symbol
   "XLXI_7/DCM_SP_inst" of type "DCM_SP".  This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "DLL_FREQUENCY_MODE" is not allowed on symbol
   "XLXI_7/DCM_SP_inst" of type "DCM_SP".  This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "DSS_MODE" is not allowed on symbol
   "XLXI_7/DCM_SP_inst" of type "DCM_SP".  This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "DUTY_CYCLE_CORRECTION" is not allowed on
   symbol "XLXI_7/DCM_SP_inst" of type "DCM_SP".  This attribute will be
   ignored.
WARNING:NgdBuild:486 - Attribute "FACTORY_JF" is not allowed on symbol
   "XLXI_7/DCM_SP_inst" of type "DCM_SP".  This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "PHASE_SHIFT" is not allowed on symbol
   "XLXI_7/DCM_SP_inst" of type "DCM_SP".  This attribute will be ignored.
WARNING:NgdBuild:486 - Attribute "STARTUP_WAIT" is not allowed on symbol
   "XLXI_7/DCM_SP_inst" of type "DCM_SP".  This attribute will be ignored.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity dcm_test2 is

 port ( 
     CLKIN       :in std_logic;   -- Clock input (from IBUFG, BUFG or DCM)
      RST        :in std_logic;
      CLK0       :out std_logic;     -- 0 degree DCM CLK ouptput
     -- CLK180      : out std_logic;-- 180 degree DCM CLK output
     -- CLK270      : out std_logic; -- 270 degree DCM CLK output
     -- CLK2X      : out std_logic;   -- 2X DCM CLK output
     -- CLK2X180    : out std_logic; -- 2X, 180 degree DCM CLK out
     -- CLK90      : out std_logic;   -- 90 degree DCM CLK output
     -- CLKDV      : out std_logic;   -- Divided DCM CLK out (CLKDV_DIVIDE)
      CLKFX      : out std_logic);   -- DCM CLK synthesis out (M/D)
     -- CLKFX180    : out std_logic); -- 180 degree CLK synthesis out
             -- DCM asynchronous reset input
end dcm_test2;

architecture Behavioral of dcm_test2 is

signal  CLKFB,GND_BIT  : std_logic;
signal LOCKED   :  std_logic; -- DCM LOCK status output
 
begin

GND_BIT <= '0';

DCM_SP_inst : DCM_SP
   generic map (
      CLKDV_DIVIDE => 2.0, --  Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
                           --     7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
      CLKFX_DIVIDE => 25,   --  Can be any interger from 1 to 32
      CLKFX_MULTIPLY => 9, --  Can be any integer from 1 to 32
      CLKIN_DIVIDE_BY_2 => FALSE, --  TRUE/FALSE to enable CLKIN divide by two feature
      CLKIN_PERIOD => 0.0, --  Specify period of input clock
      CLKOUT_PHASE_SHIFT => "NONE", --  Specify phase shift of "NONE", "FIXED" or "VARIABLE" 
      CLK_FEEDBACK => "1X",         --  Specify clock feedback of "NONE", "1X" or "2X" 
      DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or
                                             --     an integer from 0 to 15
      DLL_FREQUENCY_MODE => "LOW",     -- "HIGH" or "LOW" frequency mode for DLL
      DUTY_CYCLE_CORRECTION => TRUE, --  Duty cycle correction, TRUE or FALSE
      PHASE_SHIFT => 0,        --  Amount of fixed phase shift from -255 to 255
      STARTUP_WAIT => FALSE) --  Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE
   port map (
      CLK0 => CLK0,     -- 0 degree DCM CLK ouptput
      CLK180 => open, -- 180 degree DCM CLK output
      CLK270 => open, -- 270 degree DCM CLK output
      CLK2X => open,   -- 2X DCM CLK output
      CLK2X180 => open, -- 2X, 180 degree DCM CLK out
      CLK90 => open,   -- 90 degree DCM CLK output
      CLKDV => open,   -- Divided DCM CLK out (CLKDV_DIVIDE)
      CLKFX => CLKFX,   -- DCM CLK synthesis out (M/D)
      CLKFX180 => open, -- 180 degree CLK synthesis out
      LOCKED => open, -- DCM LOCK status output
      PSDONE => open, -- Dynamic phase adjust done output
      STATUS => open, -- 8-bit DCM status bits output
      CLKFB => open,   -- DCM clock feedback
      CLKIN => CLKIN,   -- Clock input (from IBUFG, BUFG or DCM)
      PSCLK => GND_BIT,   -- Dynamic phase adjust clock input
      PSEN => GND_BIT,     -- Dynamic phase adjust enable input
      PSINCDEC => GND_BIT, -- Dynamic phase adjust increment/decrement
      RST => RST        -- DCM asynchronous reset input
   );

end Behavioral;

[Duke Scarring (Gast)]

Im Spartan 3 heißt das Ding nur DCM. Schau Dich mal im UG607 um...

Library UNISIM;
use UNISIM.vcomponents.all;

-- DCM: Digital Clock Manager Circuit
-- Spartan-3
-- Xilinx HDL Libraries Guide, version 13.2

DCM_inst : DCM
generic map (
  CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
  -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
  CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32
  CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32
  CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
  CLKIN_PERIOD => 0.0, -- Specify period of input clock
  CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
  CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE, 1X or 2X
  DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
  -- an integer from 0 to 15
  DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
  DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
  DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
  FACTORY_JF => X"C080", -- FACTORY JF Values
  PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
  SIM_MODE => "SAFE", -- Simulation: "SAFE" vs "FAST", see "Synthesis and Simulation
  -- Design Guide" for details
  STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
port map (
  CLK0 => CLK0, -- 0 degree DCM CLK ouptput
  CLK180 => CLK180, -- 180 degree DCM CLK output
  CLK270 => CLK270, -- 270 degree DCM CLK output
  CLK2X => CLK2X, -- 2X DCM CLK output
  CLK2X180 => CLK2X180, -- 2X, 180 degree DCM CLK out
  CLK90 => CLK90, -- 90 degree DCM CLK output
  CLKDV => CLKDV, -- Divided DCM CLK out (CLKDV_DIVIDE)
  CLKFX => CLKFX, -- DCM CLK synthesis out (M/D)
  CLKFX180 => CLKFX180, -- 180 degree CLK synthesis out
  LOCKED => LOCKED, -- DCM LOCK status output
  PSDONE => PSDONE, -- Dynamic phase adjust done output
  STATUS => STATUS, -- 8-bit DCM status bits output
  CLKFB => CLKFB, -- DCM clock feedback
  CLKIN => CLKIN, -- Clock input (from IBUFG, BUFG or DCM)
  PSCLK => PSCLK, -- Dynamic phase adjust clock input
  PSEN => PSEN, -- Dynamic phase adjust enable input
  PSINCDEC => PSINCDEC, -- Dynamic phase adjust increment/decrement
  RST => RST -- DCM asynchronous reset input
);
-- End of DCM_inst instantiation

[Duke Scarring (Gast)]

P.S.: Spartan 3 != Spartan 3E != Spartan 3A

[Lothar M. (Firma: Titel) (lkmiller) (Moderator)]

Ich schrieb:
>    DCM_INST : DCM
Ramon F. schrieb:
> DCM_SP_inst : DCM_SP
Diehe dazu das da:
http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Difference-in-DCM-and-DCM-SP/td-p/38519

Fazit: nicht einfach irgendwas herkopieren und dann nebenbei auch noch 
Teile davon umbenennen...

Und: Datenblatt/Userguide lesen...