1 | /*
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2 | * File: main.c
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3 | * Author: Lena
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4 | *
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5 | * Created on 4. August 2013, 23:25
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6 | */
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7 | // PIC18F2523 Configuration Bit Settings
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8 |
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9 | #include <xc.h>
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10 |
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11 | // CONFIG1H
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12 | #pragma config OSC = HS // Oscillator Selection bits (HS oscillator)
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13 | #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
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14 | #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
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15 |
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16 | // CONFIG2L
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17 | #pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled)
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18 | #pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
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19 | #pragma config BORV = 3 // Brown Out Reset Voltage bits (Minimum setting)
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20 |
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21 | // CONFIG2H
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22 | #pragma config WDT = OFF // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
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23 | #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768)
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24 |
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25 | // CONFIG3H
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26 | #pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
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27 | #pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset)
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28 | #pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
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29 | #pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
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30 |
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31 | // CONFIG4L
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32 | #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
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33 | #pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
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34 | #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
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35 |
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36 | // CONFIG5L
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37 | #pragma config CP0 = OFF // Code Protection bit (Block 0 (000800-001FFFh) not code-protected)
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38 | #pragma config CP1 = OFF // Code Protection bit (Block 1 (002000-003FFFh) not code-protected)
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39 | #pragma config CP2 = OFF // Code Protection bit (Block 2 (004000-005FFFh) not code-protected)
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40 | #pragma config CP3 = OFF // Code Protection bit (Block 3 (006000-007FFFh) not code-protected)
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41 |
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42 | // CONFIG5H
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43 | #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
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44 | #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected)
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45 |
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46 | // CONFIG6L
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47 | #pragma config WRT0 = OFF // Write Protection bit (Block 0 (000800-001FFFh) not write-protected)
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48 | #pragma config WRT1 = OFF // Write Protection bit (Block 1 (002000-003FFFh) not write-protected)
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49 | #pragma config WRT2 = OFF // Write Protection bit (Block 2 (004000-005FFFh) not write-protected)
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50 | #pragma config WRT3 = OFF // Write Protection bit (Block 3 (006000-007FFFh) not write-protected)
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51 |
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52 | // CONFIG6H
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53 | #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
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54 | #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot block (000000-0007FFh) not write-protected)
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55 | #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
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56 |
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57 | // CONFIG7L
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58 | #pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
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59 | #pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
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60 | #pragma config EBTR2 = OFF // Table Read Protection bit (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
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61 | #pragma config EBTR3 = OFF // Table Read Protection bit (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)
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62 |
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63 | // CONFIG7H
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64 | #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) not protected from table reads executed in other blocks)
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65 |
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66 |
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67 |
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68 |
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69 | #define LED LATAbits.LA4
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70 | #define LED2 LATCbits.LC0
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71 |
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72 | int led_state = 0;
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73 |
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74 | void delay( int ms );
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75 |
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76 | //Zeitverzögerung
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77 | void delay( int ms ) {
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78 | int i=0;
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79 | //1 ms = 4000 Befehlstakte (16 MHz Quarz / 4)
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80 | for( i=0; i<ms; i++ ) {
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81 | _delay(4000);
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82 | }
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83 | }
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84 |
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85 | //void interrupt isr_high(void);
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86 |
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87 | void interrupt isr_high(void) {
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88 | if(led_state == 0)
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89 | {
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90 | LED = 1;
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91 | led_state = 1;
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92 | } else {
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93 | LED = 0;
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94 | led_state = 0;
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95 | }
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96 | INTCONbits.INT0F = 0;
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97 | INTCON3bits.INT2F = 0;
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98 | }
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99 |
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100 |
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101 | void main(void) {
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102 |
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103 |
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104 |
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105 | //Port A
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106 | LATA = 0x00; //Pegel
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107 | TRISA = 0x00; //Alle Pins von Port A sind Ausgänge
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108 | // ANSELA = 0x00; //Alle Pins von Port A sind digitale I/O's
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109 | //Port B
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110 | LATB = 0x00;
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111 | TRISB = 0xFF; //Alle Pins von Port B sind Eingänge
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112 | // ANSELB = 0x00; //Alle Pins von Port A sind digitale I/O's
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113 | //Port C
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114 | LATC = 0x00;
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115 | TRISC = 0xF0; //RC0..RC3 = Ausgänge, RC4..RC7 = Eingänge
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116 | // ANSELC = 0x30; //nur RC4 und RC5 sind analoge Eingänge
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117 |
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118 | RCONbits.IPEN = 1; //Interrupts können Prioritäten haben
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119 | INTCONbits.GIE_GIEH = 1; //Interrupts können hohe P. haben
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120 | INTCONbits.GIEL = 1;
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121 | INTCONbits.INT0IE = 1;
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122 | INTCON3bits.INT2IE = 1;
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123 | INTCON2bits.INTEDG0 = 1; //Interrupt on rising edge
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124 | INTCON2bits.INTEDG2 = 1; //Interrupt on rising edge
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125 | INTCON3bits.INT2IP = 1;
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126 |
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127 |
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128 |
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129 | while(1)
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130 | {
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131 | if(INTCON3bits.INT2F == 0) LED2 = 1;
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132 | delay(20);
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133 | LED2 = 0;
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134 | delay(20);
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135 | }
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136 |
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137 |
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138 |
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139 | }
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