1 | void adc2_init()
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2 | {
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3 | //**************************************************
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4 | //--------ADC2 INIT-------------
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5 | //**************************************************
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6 | RCC -> AHBENR |= RCC_AHBENR_ADC12EN;
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7 |
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8 | ADC2 -> CR &= ~ (ADC_CR_ADEN);// ADEN disable
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9 | ADC2 -> CR &=~(ADC_CR_ADVREGEN); // set reg to 00
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10 | ADC2 -> CR |= ADC_CR_ADVREGEN_0; // ADVREGEN 01
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11 |
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12 | ADC2 -> CR &=~(ADC_CR_ADCALDIF);// single ended
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13 | ADC2 -> CFGR |=(1<<13); //set to continous mode
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14 | ADC2 -> CR |= ADC_CR_ADCAL; // calibration
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15 |
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16 | while((ADC2-> CR & ADC_CR_ADCAL) ==1);//wait until calibration is ready
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17 |
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18 | ADC2-> CR &=~ ADC_CR_ADSTART;// ADSTART disabled
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19 | ADC2->IER |= ADC_IER_EOC;// enable end of conversion flag
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20 | ADC2-> SQR1 &=~(ADC_SQR1_SQ1);
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21 | ADC2->SQR1&=~(ADC_SQR1_L);// 1 sequenz
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22 |
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23 | ADC2-> SMPR1 &= (ADC_SMPR1_SMP1);
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24 | ADC2-> SMPR1 |= ADC_SMPR1_SMP1_0;
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25 | ADC2-> SMPR1 |= ADC_SMPR1_SMP1_1;
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26 | //ADC2-> SMPR1 |= ADC_SMPR1_SMP1_2;
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27 | /*
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28 | * SMP = 000: 1.5 ADC clock cycles
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29 | * SMP = 001: 2.5 ADC clock cycles
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30 | * SMP = 010: 4.5 ADC clock cycles
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31 | * SMP = 011: 7.5 ADC clock cycles => chosen
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32 | * SMP = 100: 19.5 ADC clock cycles
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33 | * SMP = 101: 61.5 ADC clock cycles
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34 | * SMP = 110: 181.5 ADC clock cycles
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35 | * SMP = 111: 601.5 ADC clock cycles
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36 | */
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37 |
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38 | ADC2-> CFGR &=~ (ADC_CFGR_RES);
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39 | //clock prescaler, must be there!!
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40 | RCC->CFGR2 &= ~RCC_CFGR2_ADCPRE12;
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41 | RCC->CFGR2 |= RCC_CFGR2_ADCPRE12_DIV2;
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42 |
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43 | ADC2 -> CR |= ADC_CR_ADEN;// enable ADC
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44 | while((ADC2 -> ISR & ADC_ISR_ADRD)==0);//wait until ADC is ready
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45 | }
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46 | void adc3_init()
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47 | {
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48 |
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49 | //**************************************
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50 | //--------ADC3 Init------------
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51 | //**************************************
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52 | RCC -> AHBENR |= RCC_AHBENR_ADC34EN;
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53 |
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54 | ADC3 -> CR &= ~ (ADC_CR_ADEN);// ADEN disable
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55 | ADC3 -> CR &=~(ADC_CR_ADVREGEN); // set reg to 00
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56 | ADC3 -> CR |= ADC_CR_ADVREGEN_0; // ADVREGEN 0
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57 |
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58 | ADC3 -> CR &=~(ADC_CR_ADCALDIF);// single ended
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59 | ADC3 -> CFGR |=(1<<13); //set to continous mode
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60 | ADC3 -> CR |= ADC_CR_ADCAL; // calibration
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61 |
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62 | while((ADC3-> CR & ADC_CR_ADCAL) ==1);//wait until calibration is ready
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63 |
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64 | ADC3-> CR &=~ ADC_CR_ADSTART;// ADSTART disabled
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65 | ADC3->IER |= ADC_IER_EOC;// enable end of conversion flag
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66 | ADC3-> SQR1 &=~(ADC_SQR1_SQ1);
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67 | ADC3->SQR1&=~(ADC_SQR1_L);// 1 sequenz
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68 |
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69 | ADC3-> SMPR1 &= (ADC_SMPR1_SMP1);
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70 | ADC3-> SMPR1 |= ADC_SMPR1_SMP1_0;
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71 | ADC3-> SMPR1 |= ADC_SMPR1_SMP1_1;
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72 | //ADC3-> SMPR1 |= ADC_SMPR1_SMP1_2;
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73 | /*
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74 | * SMP = 000: 1.5 ADC clock cycles
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75 | * SMP = 001: 2.5 ADC clock cycles
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76 | * SMP = 010: 4.5 ADC clock cycles
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77 | * SMP = 011: 7.5 ADC clock cycles => chosen
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78 | * SMP = 100: 19.5 ADC clock cycles
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79 | * SMP = 101: 61.5 ADC clock cycles
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80 | * SMP = 110: 181.5 ADC clock cycles
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81 | * SMP = 111: 601.5 ADC clock cycles
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82 | */
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83 |
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84 |
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85 | ADC3-> CFGR &=~ (ADC_CFGR_RES); //data resolution
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86 | //clock prescaler, must be there!!
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87 | RCC->CFGR2 &= ~RCC_CFGR2_ADCPRE34; //erase register
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88 | RCC->CFGR2 |= RCC_CFGR2_ADCPRE34_DIV2; // set precaler; division 2
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89 | //RCC->CFGR2 |= RCC_CFGR2_ADCPRE34_NO;//use AHB clock
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90 |
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91 | ADC3 -> CR |= ADC_CR_ADEN;// enable ADC
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92 | while((ADC3 -> ISR & ADC_ISR_ADRD)==0);//wait until ADC is ready
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93 |
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94 | }
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95 | void adc4_init()
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96 | {
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97 | //**************************************************
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98 | //--------ADC4 INIT-------------
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99 | //**************************************************
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100 | RCC -> AHBENR |= RCC_AHBENR_ADC34EN;
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101 |
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102 | ADC4 -> CR &= ~ (ADC_CR_ADEN);// ADEN disable
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103 | ADC4 -> CR &=~(ADC_CR_ADVREGEN); // set reg to 00
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104 | ADC4 -> CR |= ADC_CR_ADVREGEN_0; // ADVREGEN 0
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105 |
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106 | ADC4 -> CR &=~(ADC_CR_ADCALDIF);// single ended
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107 | ADC4 -> CFGR |=(1<<13); //set to continous mode
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108 | ADC4 -> CR |= ADC_CR_ADCAL; // calibration
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109 |
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110 | while((ADC4-> CR & ADC_CR_ADCAL) ==1);//wait until calibration is ready
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111 |
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112 | ADC4-> CR &=~ ADC_CR_ADSTART;// ADSTART disabled
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113 | ADC4->IER |= ADC_IER_EOC;// enable end of conversion flag
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114 | ADC4-> SQR1 &=~(ADC_SQR1_SQ1);
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115 | ADC4->SQR1&=~(ADC_SQR1_L);// 1 sequenz
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116 |
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117 | ADC4-> SMPR1 &= (ADC_SMPR1_SMP1);
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118 | ADC4-> SMPR1 |= ADC_SMPR1_SMP1_0;
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119 | ADC4-> SMPR1 |= ADC_SMPR1_SMP1_1;
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120 | //ADC3-> SMPR1 |= ADC_SMPR1_SMP1_2;
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121 | /*
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122 | * SMP = 000: 1.5 ADC clock cycles
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123 | * SMP = 001: 2.5 ADC clock cycles
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124 | * SMP = 010: 4.5 ADC clock cycles
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125 | * SMP = 011: 7.5 ADC clock cycles => chosen
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126 | * SMP = 100: 19.5 ADC clock cycles
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127 | * SMP = 101: 61.5 ADC clock cycles
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128 | * SMP = 110: 181.5 ADC clock cycles
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129 | * SMP = 111: 601.5 ADC clock cycles
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130 | */
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131 |
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132 | ADC4-> CFGR &=~ (ADC_CFGR_RES);
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133 | //clock prescaler, must be there!!
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134 | RCC->CFGR2 &= ~RCC_CFGR2_ADCPRE34;
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135 | RCC->CFGR2 |= RCC_CFGR2_ADCPRE34_DIV2;
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136 |
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137 |
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138 | ADC4 -> CR |= ADC_CR_ADEN;// enable ADC
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139 | while((ADC4 -> ISR & ADC_ISR_ADRD)==0);//wait until ADC is ready
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140 |
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141 | }
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