VHDL Frequenzteiler undefinierte Variable

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

use ieee.numeric_std.all;

use ieee.math_real.all;

--========================================

entity CLK_ENA is 

  generic (cnt_max_g : natural);

  port

  (

    RESET_n : in  std_logic;

    CLK     : in  std_logic;

    ENA     : out std_logic

  );

end CLK_ENA;

architecture rtl of CLK_ENA is

  constant cbw : natural := natural(log2(real(cnt_max_g))+1.0);

  signal counter : natural range 0 to 2**cbw-1;

begin

  process (CLK, RESET_n)

    begin

      if(RESET_n = '0') then

        counter <= 0;

        ENA <= '0';

      else if (CLK' event and CLK = '1') then

        if (counter < cnt_max_g) then

          ENA <= '1';

          counter <= counter +1;

        else

          ENA <= '1';

          counter <= 0;

        end if;

      end if;

      end if;

  end process;

end rtl;