1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use ieee.numeric_std.ALL;
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4 |
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5 | entity vga_viereck_ps2 is
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6 | port(
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7 | clk50_in : in std_logic;
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8 | hs_out : out std_logic;
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9 | vs_out : out std_logic;
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10 |
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11 | ps2_clk : in std_logic;
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12 | ps2_data : in std_logic;
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13 |
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14 | led_g : OUT STD_LOGIC_VECTOR(7 downto 0);
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15 |
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16 | red_out : OUT STD_LOGIC_VECTOR(3 downto 0);
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17 | green_out : OUT STD_LOGIC_VECTOR(3 downto 0);
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18 | blue_out : OUT STD_LOGIC_VECTOR(3 downto 0)
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19 | );
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20 | end vga_viereck_ps2;
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21 |
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22 | architecture behavioral of vga_viereck_ps2 is
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23 |
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24 | signal clk25 : std_logic:='0';
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25 | signal hcounter : integer range 0 to 1000 := 0;
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26 | signal vcounter : integer range 0 to 1000 := 0;
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27 | signal links_neu : integer range 0 to 1000 := 100;
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28 | signal rechts_neu : integer range 0 to 1000 := 120;
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29 | signal oben_neu : integer range 0 to 1000 := 100;
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30 | signal unten_neu : integer range 0 to 1000 := 120;
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31 | signal links : integer range 0 to 1000 := 0;
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32 | signal rechts : integer range 0 to 1000 := 0;
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33 | signal oben : integer range 0 to 1000 := 0;
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34 | signal unten : integer range 0 to 1000 := 0;
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35 | signal add_sub : integer range 0 to 100 := 1;
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36 | signal c : integer range 0 to 500000 := 0;
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37 | signal red : STD_LOGIC_VECTOR(3 downto 0);
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38 | signal green : STD_LOGIC_VECTOR(3 downto 0);
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39 | signal blue : STD_LOGIC_VECTOR(3 downto 0);
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40 |
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41 | signal ps2_clk_int: std_logic;
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42 | signal ps2_data_int: std_logic;
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43 |
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44 | signal ps2_clk_falling_edge: std_logic;
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45 | signal last_ps2_clk: std_logic;
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46 |
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47 | signal started: std_logic;
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48 |
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49 | signal count : integer range 0 to 10:=0;
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50 | signal data : std_logic_vector(9 downto 0);
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51 | signal vga_data : STD_LOGIC_VECTOR(7 downto 0);
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52 | signal key_released : std_logic;------------------------------------ für die Abfrage
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53 |
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54 | begin
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55 |
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56 | process (clk50_in)
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57 | begin
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58 | if rising_edge(clk50_in) then
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59 | if vga_Data ="00000101" then
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60 | red<="1111";
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61 | green<="0000";
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62 | blue<="0000";
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63 | end if;
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64 |
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65 | if vga_Data ="00000110" then
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66 | red<="0000";
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67 | green<="1111";
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68 | blue<="0000";
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69 | end if;
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70 |
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71 | if vga_Data ="00000100" then
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72 | red<="0000";
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73 | green<="0000";
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74 | blue<="1111";
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75 | end if;
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76 | end if;
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77 | end process;
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78 |
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79 | process (clk50_in)
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80 | begin
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81 | if rising_edge(clk50_in) then
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82 | if (clk25 = '0') then
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83 | clk25 <= '1';
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84 | else
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85 | clk25 <= '0';
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86 | end if;
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87 | end if;
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88 | end process;
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89 |
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90 | process(clk50_in)
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91 | begin
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92 | if rising_edge(clk50_in) then
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93 | if (c<200000) then
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94 | c <= c+1;
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95 | else
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96 | ----------------------------------------------------
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97 | if vga_Data = "11110000" then -- 0xF0
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98 | key_released <= '1'; ----- neu reingesetzt, wir als Fehler rausgeschmissen
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99 | end if;
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100 | ------------------------------------------------------
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101 | if vga_Data ="01110100" then -- rechts
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102 | rechts_neu <= rechts_neu+add_sub;
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103 | links_neu <= links_neu+add_sub;
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104 | if rechts_neu = 640 then
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105 | rechts_neu <=640;
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106 | links_neu <=620;
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107 | end if;
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108 | end if;
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109 |
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110 | if vga_Data ="01101011" then -- links
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111 | rechts_neu <= rechts_neu-add_sub;
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112 | links_neu <= links_neu-add_sub;
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113 | if links_neu = 0 then
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114 | rechts_neu <=20;
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115 | links_neu <=0;
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116 | end if;
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117 | end if;
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118 |
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119 | if vga_Data ="01110010" then -- unten
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120 | unten_neu <= unten_neu+add_sub;
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121 | oben_neu <= oben_neu+add_sub;
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122 | if unten_neu = 480 then
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123 | unten_neu <=480;
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124 | oben_neu <=460;
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125 | end if;
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126 | end if;
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127 |
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128 | if vga_Data ="01110101" then -- oben
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129 | unten_neu <= unten_neu-add_sub;
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130 | oben_neu <= oben_neu-add_sub;
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131 | if oben_neu = 0 then
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132 | unten_neu <=20;
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133 | oben_neu <=0;
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134 | end if;
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135 | end if;
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136 |
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137 | c <= 0;
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138 | end if;
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139 | end if;
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140 | end process;
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141 |
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142 | process (clk50_in)
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143 | begin
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144 | if rising_edge(clk50_in) then
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145 | if clk25 = '1' then
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146 | if (hcounter >= links) and (hcounter < rechts) and (vcounter >= oben) and (vcounter < unten) then
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147 | red_out<= red;
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148 | green_out<=green;
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149 | blue_out<=blue;
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150 | else
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151 | red_out<="0000";
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152 | green_out<="0000";
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153 | blue_out<="0000";
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154 | end if;
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155 | end if;
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156 | end if;
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157 | end process;
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158 |
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159 | process (clk50_in)
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160 | begin
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161 | if rising_edge(clk50_in) then
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162 | if clk25 = '1' then
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163 | if hcounter >= (639+16) and hcounter <= (639+16+96) then
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164 | hs_out <= '0';
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165 | else
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166 | hs_out <= '1';
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167 | end if;
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168 |
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169 | if vcounter >= (479+10) and vcounter <= (479+10+2) then
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170 | vs_out <= '0';
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171 | else
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172 | vs_out <= '1';
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173 | end if;
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174 |
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175 | --- horizontal counts from 0 to 799
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176 | hcounter <= hcounter+1;
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177 |
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178 | if hcounter = 799 then
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179 | vcounter <= vcounter+1;
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180 | hcounter <= 0;
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181 | end if;
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182 |
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183 | --- vertical counts from 0 to 524
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184 | if vcounter = 524 then
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185 | rechts <= rechts_neu;
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186 | links <= links_neu;
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187 | oben <= oben_neu;
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188 | unten <= unten_neu;
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189 | vcounter <= 0;
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190 | end if;
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191 | end if;
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192 | end if;
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193 | end process;
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194 |
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195 | process(clk50_in)
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196 | begin
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197 | if rising_edge(clk50_in) then
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198 | ps2_clk_int <= ps2_clk;
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199 | ps2_data_int <= ps2_data;
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200 | end if;
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201 | end process;
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202 |
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203 | process(clk50_in)
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204 | begin
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205 | if rising_edge(clk50_in) then
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206 | last_ps2_clk <= ps2_clk_int;
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207 |
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208 | if last_ps2_clk = '1' and ps2_clk_int = '0' then
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209 | ps2_clk_falling_edge <= '1';
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210 | else
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211 | ps2_clk_falling_edge <= '0';
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212 | end if;
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213 | end if;
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214 | end process;
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215 |
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216 | process(clk50_in)
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217 | begin
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218 | if rising_edge(clk50_in) then
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219 | if ps2_clk_falling_edge = '1' and ps2_data_int = '0' then
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220 | started <= '1';
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221 | end if;
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222 |
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223 | if count = 10 then
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224 | started <= '0';
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225 | end if;
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226 | end if;
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227 | end process;
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228 |
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229 | process(clk50_in)
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230 | begin
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231 | if rising_edge(clk50_in) then
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232 | if ps2_clk_falling_edge = '1' and started = '1' then
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233 | count <= count + 1;
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234 | data <= ps2_data_int & data(9 downto 1);
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235 | end if;
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236 |
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237 | if count = 10 then
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238 | count <= 0;
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239 | end if;
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240 | end if;
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241 | end process;
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242 |
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243 | process(clk50_in)
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244 | begin
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245 | if rising_edge(clk50_in) then
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246 | if key_released = '1' then ---------------------------------------------
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247 | vga_data <= "00000000"; ---- dieses wird anerkannt.
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248 | key_released <= '0'; ---------------------------------------------
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249 | else
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250 | vga_data <= data(7 downto 0);
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251 | led_g <= data(7 downto 0);
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252 | end if;
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253 | end if;
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254 | end process;
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255 |
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256 | end behavioral;
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