Hallo zusammen! Ich so etwas möglich, dass ich anstatt:
1 | -- ...
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2 | out : out bit_vector(7 downto 0) |
3 | -- ...
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4 | signal iout: std_logic_vector (255 downto 0); |
5 | -- ...
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6 | |
7 | -- ...
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8 | out <= to_bitvector( iout(255 downto 248) ); |
9 | -- ...
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10 | out <= to_bitvector( iout(247 downto 240) ); |
11 | -- ...
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So etwas schreiben kann?
1 | -- ...
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2 | out : out bit_vector(7 downto 0) |
3 | -- ...
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4 | signal iout: std_logic_vector (255 downto 0); |
5 | signal k: integer:= 0; |
6 | -- ...
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7 | |
8 | -- ...
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9 | out <= to_bitvector( iout( (255-k*8) downto (248-k*8) ) ); |
10 | -- ...
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