Hallo, guten Tag.
Ich bekomme es nicht hin, RS_Data in das speicher_ram zu packen.
Ich habe meine VHDL wieder verworfen, weil es keinen richtigen Anfang
gibt.
Wer kann da mal helfen?
Die RS232-Empfangsroutine funktioniert im Test weil die LED so blinken
wie die Daten vorhanden sind.
Danke.
Gruss
1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.NUMERIC_STD.ALL;
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4 |
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5 | entity ram_array is
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6 | Generic ( Quarz_Taktfrequenz : integer := 50000000;
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7 | Baudrate : integer := 9600
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8 | );
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9 | port(
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10 | clk : in std_logic;
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11 | RXD : in STD_LOGIC;
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12 | );
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13 | end ram_array;
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14 |
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15 | architecture Behavioral of ram_array is
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16 |
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17 | signal rxd_sr : std_logic_vector (3 downto 0) := "1111";
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18 | signal rxsr : std_logic_vector (7 downto 0) := "00000000";
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19 | signal rxbitcnt : integer range 0 to 9 := 9;
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20 | signal rxcnt : integer range 0 to (Quarz_Taktfrequenz/Baudrate)-1;
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21 | signal RX_Data : STD_LOGIC_VECTOR (7 downto 0);
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22 | signal RX_Busy : STD_LOGIC;
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23 |
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24 | Type Ram128x8 is ARRAY (0 to 127) OF unsigned(7 downto 0);
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25 | signal speicher_ram : Ram128x8;
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26 |
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27 | signal RamAddr: integer range 0 to 127 := 0;
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28 |
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29 | begin
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30 |
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31 | process(clk)
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32 | begin
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33 | .................
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34 | .................
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35 | end process;
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36 |
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37 | process(clk)
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38 | begin
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39 | if rising_edge(clk) then
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40 | rxd_sr <= rxd_sr(rxd_sr'left-1 downto 0) & RXD;
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41 | if (rxbitcnt<9) then
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42 | if(rxcnt<(Quarz_Taktfrequenz/Baudrate)-1) then
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43 | rxcnt <= rxcnt+1;
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44 | else
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45 | rxcnt <= 0;
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46 | rxbitcnt <= rxbitcnt+1;
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47 | rxsr <= rxd_sr(rxd_sr'left-1) & rxsr(rxsr'left downto 1);
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48 | end if;
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49 | else
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50 | if (rxd_sr(3 downto 2) = "10") then
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51 | rxcnt <= ((Quarz_Taktfrequenz/Baudrate)-1)/2;
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52 | rxbitcnt <= 0;
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53 | end if;
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54 | end if;
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55 | end if;
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56 | end process;
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57 |
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58 | RX_Data <= rxsr;
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59 | RX_Busy <= '1' when (rxbitcnt<9) else '0';
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60 | end Behavioral;
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