Cyclone IV + Reading from DIP Switches

[Enrique P. (flote21)]

Hello,

I am having some problems to read the '0' logic values from the DIP 
Swithches with an ALTERA Cyclone IV FPGA. I always read '1' logic 
whatever position is configured in the switches

DIP Switches are connected in this way, When they are ON, both sides of 
the SW are connected to VDD throughr a resistor. Therefore the FPGA read 
"VDD".
And when they are OFF, the pin of the FPGA is open circuit. I mean there 
is not any connection to ground through the SW. Simply, the DIP SW open 
the circuit and leave the FPGA pin without any connection...I measured 
in the pon of the FPGA and I got 20mV. In theory this should be read 
like a '0' logic, right? What could be the problem?

Is there any special constraint that I have to add to my pin assgnments 
file?

Note: I've also tried to connect manually the PIN of the FPGA to GND and 
then the FPGA read '0'.

Thanks a lot!

[derElf (Gast)]

You need to add a pulldown resistor externally or internallly.

[Enrique P. (flote21)]

Hi!

thank you very much for your

But In Altera FPGAs it is impossible to set up programmable pull DOWN 
resistors. right?

thanks

[Michael (Gast)]

What evalboard you are using, the DE0-Nano?

[Enrique (Gast)]

Hi

I am using a custom board designed by one of the engineers of my 
company. We are using this model of Cyclone IV: EP4CE15F23C7N. I think 
that it is no possible to set up internal pull down resistors...

Thanks

[Lattice User (Gast)]

Enrique schrieb:
> Hi
>
> I am using a custom board designed by one of the engineers of my
> company. We are using this model of Cyclone IV: EP4CE15F23C7N. I think
> that it is no possible to set up internal pull down resistors...
>

Then you should call for a flocking, not below 100 hits.

This

> DIP Switches are connected in this way, When they are ON, both sides of
> the SW are connected to VDD throughr a resistor. Therefore the FPGA read
> "VDD".

is not how you connect a DIP Switch.


Since the Cyclone IV indeed has no pulldown capability, you need to add 
an external resistor.

[./. (Gast)]

> I think
> that it is no possible to set up internal pull down resistors...
You are right. There is no such option.

You may switch one pin to 'out' and '0'.
Then You have to switch this permanent on.

Then You will be able to read '0' from the other switches.

Is Your coworker chinese?

The same mistake was made on a Cyclone evalboard from China...

I used SMD resistors and a piece of wire for a external pull down.

[Enrique P. (flote21)]

hi thanks for your quick answer.

I was thinking about another smarter solution. All the possible
solutions given need to modifz the HW. So then I would like to do
something which not requires a big modifiation with a lot of resistances
and wires...

This is the current connection between the FPGA and the DiP SW:

         |               _3.3v
         |               |
         |              _|_
         |             |  |
         |             |__|
         |               |
         |    /          |
 FPGA ___|___/  _________|
         |
         |
         |

Then I could remove the 3.3V, tie to ground this and place a 0ohm
resistance. Therefore, using the internal weak pull-up resistance of the 
FPGA I will have the DIP SW working in the way that I want...

                                  _0v
                 |                |
        3.3v     |               _|_
         _|_     |              |  | Ohm
 weak    | |     |              |__|
 pull-up |_|     |                |
          |      |     /          |
        _ |_FPGA_|____/  _________|
                 |
                 |
                 |

But I am afraid about one issue. Maybe the internal weak pull-up
resistance of the FPGA is too weak and it is not able to put a logic ¨1¨
when the SW is closed..
What do you think?>
Thanks

[Lattice User (Gast)]

Enrique schrieb im Beitrag #3687085:
> hi thanks for your quick answer.
>
>
> Then could I remove the 3.3V, tie to ground this and place a 0ohm
> resistance. Then using the internal weak pull-up resistance of the FPGA
> I will have the DIP SW working in the way that I want...
>
>                                  _0v
>                 |                |
>        3.3v     |               _|_
>         _|_     |              |  | Ohm
> weak    | |     |              |__|
> pull-up |_|     |                |
>          |      |     /          |
>        _ |_FPGA_|____/  _________|
>                 |
>                 |
>                 |
>
> But I am afraid about one issue, Maybe the internal weak pull-up
> resistance of the FPGA is too weak and it is not able to put a logic ¨1¨
> when the SW is closed..
>
> What do you think?
>

This is fine, as it resembles the usual way to do this. Switch to GND 
and pullup to VCC. But make sure that in a respin of the board an 
external resitor is added for better noise margin. (There will be a 
respin, as you will probably find more bugs)

Be aware, for switch closed you will read a 0, for switch open you will 
read a 1! This is inverted from the original intention.

[Enrique P. (flote21)]

it works!!!! Nices solution this!!! Thanks for ur ideas!!!