errors in my VHDL program

[Louis L. (louivans)]

Hi,

I try to make a program in VHDL but I have some errors. Firt of all I 
Want to do an infiny loop, I think in my program it's would be work but 
I'm not sure. I used a process, if I well understand the process is a 
block which restart at the begining's process when it arrives at the end 
wihtout wait condition ?

I have some output errors, it's said that it can't read the output, 
maybe it's because I define the output as real. I'm not sure if it's 
good to do that ?

You will find the program attached.

[dsPICeinsteiger (Gast)]

Do you actually want to synthesize the program or should it only be 
simulated?

An infinity loop as you tried to do it ist not possible in any case, as 
time never progresses. You have to add a wait or a sensitivity list to 
your process.

[Louis L. (louivans)]

for the moment I just want to simulate.

In fact I want to create a chaotic signal, so the outputs X,Y and Z 
change at each end of the process. And during the process I ned the 
outputs to give a new value of them. I have the matlab program which 
work, it's attached.

for what you said (add a wait or sensitivity list) I don't know why. I 
just want when the process is finished, it's come back at the begening 
of the process, like a FOR loop in programmation.

And do you think it's good to put the outpouts as real ?

[dsPICeinsteiger (Gast)]

As I said, you need to allow for time to progress. VHDL is an event 
based language, the current program creates an event at time 0 
indefinitly. This way you will never see any output.

If you want to see a chaotic signal, you could just output a nev value 
periodically? Just add a e.g. wait 1 ns; to your loop?

As for your second error, you can not read outputs, which X, Y and Z are 
defined as. Create an internal copy of the signals and assign X, Y and Z 
their respective values.

Real is not systhesizable for the majority of cases, but should not be a 
problem for simulation (depending on your tool).

[Louis L. (louivans)]

OK I know what you mean I add "wait for 1 ns;" at the end of the process 
and I have lees errors than before, thanks for that.

For the second erros, I don't understand what you said, how can I create 
an internal copy of the signals ?
It's not what I did at the beginning of the process ?
y1m := X;
y2m := Y;
y3m := Z;

[foo (Gast)]

VHDL is a H ardware D escription L anguage and not a progamming 
language.

It looks similar to am programming language, but you are describing 
hardware.

Please du some tutorial stuff on this topic, untill you realized the 
diffenence.

[dsPICeinsteiger (Gast)]

X, Y and Z are signals, so assignments use the <= operator.

But as foo realized, there are extremely grave errors in your program, 
which clearly show that you are not familiar with the basic concepts of 
VHDL. Of course correcting your program would be no problem, but if you 
intend to learn something, please read some tutorials on the basics.

[foo (Gast)]

And next Time: Please poste the errormessages too. Its much faster to 
debug with, nobody wants to read many lines of code or eaven pick the 
file and set it up in another Toolchain.

[Lothar M. (Firma: Titel) (lkmiller) (Moderator)]

foo schrieb:
> And next Time: Please post ...
... in the English forum!
http://embdev.net/forum/fpga-vhdl-verilog

[Louis L. (louivans)]

I managed all the errors, I did what dsPICeinsteiger said ( Create an 
internal copy of the signals and assign X, Y and Z
their respective values)

thanks for your help
I know I don't have the skills in VHDL but it's help when we ask on 
forum.
I create the topic here because the english forum seems to be a little 
dead.

[Lothar M. (Firma: Titel) (lkmiller) (Moderator)]

Louis Louis schrieb:
> I create the topic here because the english forum seems to be a little
> dead.
It isn't. Its visible from and included in the German forum.