hi ich hab gerade ein Problem mit dem I2S Interface vom LPC1768 und einem wolfson Codec ( WM8510 ) Der I2S am LPC hat I2SRX_CLK Receive Clock. A clock signal used to synchronize the transfer of data on the receive channel. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S bus specification. I2SRX_WS Receive Word Select. Selects the channel from which data is to be received. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S bus specification. WS = 0 indicates that data is being received by channel 1 (left channel). WS = 1 indicates that data is being received by channel 2 (right channel). I2SRX_SDA Receive Data. Serial data, received MSB first. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S bus specification. RX_MCLK Output Optional master clock output for the I2S receive function. I2STX_CLK Transmit Clock. A clock signal used to synchronize the transfer of data on the transmit channel. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S bus specification. I2STX_WS Transmit Word Select. Selects the channel to which data is being sent. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S bus specification. WS = 0 indicates that data is being sent to channel 1 (left channel). WS = 1 indicates that data is being sent to channel 2 (right channel). I2STX_SDA Transmit Data. Serial data, sent MSB first. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S bus specification. TX_MCLK Output Optional master clock output for the I2S transmit function. am wolfson fehlen natürliche inige pins .. weil mono ADCDAT - Digital Output ADC Digital Audio Data Output DACDAT - Digital Input DAC Digital Audio Data Input FRAME - Digital Input/Output DAC and ADC Sample Rate Clock or Frame sync BCLK - Digital Input/Output Digital Audio Port Clock MCLK - Digital Input Master Clock Input demnach müsste ich die WS am LPC hart verdrahten oder? zB pullup gegen VCC oder pulldown GND I2SRX_WS --> pulldown -->0 -> left channel I2SRX_SDA --> ADCDAT I2STX_WS --> offen I2STX_SDA --> DACDAT TX_MCLK --> MCLK und hier bin ich mir nicht sicher : I2STX_CLK --> BCLK I2SRX_CLK --> FRAME hat schonmal jemand sowas gemacht ? oder versteht zumindestd ie I2S schnittstelle ? danke
Schaltplan für LPC4078 (pin-kompatibel zu LPC1768 und WM8903: http://www.support.code-red-tech.com/CodeRedWiki/RDB4078Docs Demo-SW für I2S gibt es da auch.
> http://www.support.code-red-tech.com/CodeRedWiki/RDB4078Docs Ohne Login findet man da nicht viel. Das hier? http://www.support.code-red-tech.com/CodeRedWiki/RDB4078Support
./. schrieb: > Ohne Login findet man da nicht viel. Was für ein Login? Click auf: RDB4078 Schematic (PDF)
Lothar schrieb: > Schaltplan für LPC4078 (pin-kompatibel zu LPC1768 und WM8903: > > http://www.support.code-red-tech.com/CodeRedWiki/RDB4078Docs > > Demo-SW für I2S gibt es da auch. das hilft mir schonmal sehr viel weiter. vielen Dank ADCDAT -> I2SRX_SDA DACDAT -> I2STX_SDA FRAME -> I2SRX_WS BCLK -> I2SRX_CLK MCLK -> RX_MCLK
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