1 | ; CONFIG1L
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2 | CONFIG PLLSEL = PLL3X ; PLL Selection (3x clock multiplier)
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3 | CONFIG CFGPLLEN = OFF ; PLL Enable Configuration bit (PLL Disabled (firmware controlled))
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4 | CONFIG CPUDIV = NOCLKDIV ; CPU System Clock Postscaler (CPU uses system clock (no divide))
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5 | CONFIG LS48MHZ = SYS48X8 ; Low Speed USB mode with 48 MHz system clock (System clock at 48 MHz, USB clock divider is set to 8)
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6 |
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7 | ; CONFIG1H
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8 | CONFIG FOSC = INTOSCIO ; Oscillator Selection (Internal oscillator)
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9 | CONFIG PCLKEN = OFF ; Primary Oscillator Shutdown (Primary oscillator shutdown firmware controlled)
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10 | CONFIG FCMEN = ON ; Fail-Safe Clock Monitor (Fail-Safe Clock Monitor enabled)
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11 | CONFIG IESO = OFF ; Internal/External Oscillator Switchover (Oscillator Switchover mode disabled)
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12 |
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13 | ; CONFIG2L
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14 | CONFIG nPWRTEN = OFF ; Power-up Timer Enable (Power up timer disabled)
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15 | CONFIG BOREN = SBORDIS ; Brown-out Reset Enable (BOR enabled in hardware (SBOREN is ignored))
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16 | CONFIG BORV = 190 ; Brown-out Reset Voltage (BOR set to 1.9V nominal)
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17 | CONFIG nLPBOR = ON ; Low-Power Brown-out Reset (Low-Power Brown-out Reset enabled)
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18 |
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19 | ; CONFIG2H
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20 | CONFIG WDTEN = OFF ; Watchdog Timer Enable bits (WDT disabled in hardware (SWDTEN ignored))
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21 | CONFIG WDTPS = 32768 ; Watchdog Timer Postscaler (1:32768)
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22 |
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23 | ; CONFIG3H
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24 | CONFIG CCP2MX = RC1 ; CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
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25 | CONFIG PBADEN = OFF ; PORTB A/D Enable bit (PORTB<5:0> pins are configured as digital I/O on Reset)
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26 | CONFIG T3CMX = RC0 ; Timer3 Clock Input MUX bit (T3CKI function is on RC0)
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27 | CONFIG SDOMX = RC7 ; SDO Output MUX bit (SDO function is on RC7)
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28 | CONFIG MCLRE = ON ; Master Clear Reset Pin Enable (MCLR pin enabled; RE3 input disabled)
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29 |
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30 | ; CONFIG4L
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31 | CONFIG STVREN = ON ; Stack Full/Underflow Reset (Stack full/underflow will cause Reset)
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32 | CONFIG LVP = OFF ; Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
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33 | CONFIG XINST = OFF ; Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled)
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34 |
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35 | ; CONFIG5L
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36 | CONFIG CP0 = OFF ; Block 0 Code Protect (Block 0 is not code-protected)
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37 | CONFIG CP1 = OFF ; Block 1 Code Protect (Block 1 is not code-protected)
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38 | CONFIG CP2 = OFF ; Block 2 Code Protect (Block 2 is not code-protected)
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39 | CONFIG CP3 = OFF ; Block 3 Code Protect (Block 3 is not code-protected)
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40 |
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41 | ; CONFIG5H
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42 | CONFIG CPB = OFF ; Boot Block Code Protect (Boot block is not code-protected)
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43 | CONFIG CPD = OFF ; Data EEPROM Code Protect (Data EEPROM is not code-protected)
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44 |
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45 | ; CONFIG6L
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46 | CONFIG WRT0 = OFF ; Block 0 Write Protect (Block 0 (0800-1FFFh) is not write-protected)
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47 | CONFIG WRT1 = OFF ; Block 1 Write Protect (Block 1 (2000-3FFFh) is not write-protected)
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48 | CONFIG WRT2 = OFF ; Block 2 Write Protect (Block 2 (04000-5FFFh) is not write-protected)
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49 | CONFIG WRT3 = OFF ; Block 3 Write Protect (Block 3 (06000-7FFFh) is not write-protected)
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50 |
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51 | ; CONFIG6H
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52 | CONFIG WRTC = OFF ; Configuration Registers Write Protect (Configuration registers (300000-3000FFh) are not write-protected)
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53 | CONFIG WRTB = OFF ; Boot Block Write Protect (Boot block (0000-7FFh) is not write-protected)
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54 | CONFIG WRTD = OFF ; Data EEPROM Write Protect (Data EEPROM is not write-protected)
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55 |
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56 | ; CONFIG7L
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57 | CONFIG EBTR0 = OFF ; Block 0 Table Read Protect (Block 0 is not protected from table reads executed in other blocks)
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58 | CONFIG EBTR1 = OFF ; Block 1 Table Read Protect (Block 1 is not protected from table reads executed in other blocks)
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59 | CONFIG EBTR2 = OFF ; Block 2 Table Read Protect (Block 2 is not protected from table reads executed in other blocks)
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60 | CONFIG EBTR3 = OFF ; Block 3 Table Read Protect (Block 3 is not protected from table reads executed in other blocks)
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61 |
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62 | ; CONFIG7H
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63 | CONFIG EBTRB = OFF ; Boot Block Table Read Protect (Boot block is not protected from table reads executed in other blocks)
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