Hm ... keine Ahnung was flasch war, Testbench lief natürlich auch nicht
also hab ich mal ein Minimalbeispiel aufgemacht und das funktioniert
prima. Edit: Aber wenn ich das in mein erweitertes Signalgeneratormodul
einbaue gibt es wieder diese Fehler. Also zuerst das funktionierende
Minimalbeispiel, dann die Testbench dazu und danach das was nicht
funktioniert.
Der Sinusgenerator als Minimalbeispiel. (1024 Punkte je 10 Bit):
1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.numeric_std.all;
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4 | use ieee.math_real.all;
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5 |
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6 | entity sin_minimal is Port(
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7 | clk : in std_logic;
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8 | output : out std_logic_vector(9 downto 0));
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9 | end sin_minimal;
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10 |
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11 | architecture Behavioral of sin_minimal is
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12 |
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13 | signal pointer: unsigned(9 downto 0):=(others => '0');
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14 | type Rom512x9 is array (0 to 511) of unsigned(8 downto 0);
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15 | signal Sinus_Rom : Rom512x9;
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16 |
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17 | begin
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18 |
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19 | tabel : for I in 0 to 511 generate
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20 | Sinus_Rom(I) <= to_unsigned(integer( sin(2.0*MATH_PI*(real(I)+0.5)/1024.0) *511.5),9);
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21 | end generate;
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22 |
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23 | process begin
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24 | wait until rising_edge(clk);
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25 | pointer <= pointer +1;
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26 |
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27 | if pointer(9) = '0' then
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28 | output <= std_logic_vector(to_unsigned(511 + to_integer(Sinus_Rom(to_integer(pointer(8 downto 0)))),10));
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29 | else
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30 | output <= std_logic_vector(to_unsigned(511 - to_integer(Sinus_Rom(to_integer(pointer(8 downto 0)))),10));
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31 | end if;
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32 |
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33 | end process;
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34 |
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35 | end Behavioral;
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1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 |
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4 | entity sin_minimal_bench is
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5 | end sin_minimal_bench;
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6 |
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7 | architecture Behavioral of sin_minimal_bench is
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8 |
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9 | component sin_minimal is Port(
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10 | clk : in STD_LOGIC;
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11 | output : out std_logic_vector(9 downto 0));
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12 | end component;
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13 |
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14 | signal clk_in: std_logic:='0';
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15 | signal output_out: std_logic_vector(9 downto 0):=(others => '0');
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16 | constant clk_in_half_period : time := 5 ns;
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17 |
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18 | begin
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19 |
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20 | s0: sin_minimal port map(
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21 | clk => clk_in,
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22 | output => output_out);
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23 |
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24 | clk_in <= not clk_in after clk_in_half_period;
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25 |
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26 | end Behavioral;
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Und hier das was nicht funktioniert:
1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.numeric_std.all;
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4 | use ieee.math_real.all;
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5 |
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6 | entity siggen is port(
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7 | clk : in std_logic;
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8 | sigtype : in std_logic_vector(12 downto 10);
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9 | freq : in std_logic_vector(9 downto 0);
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10 | output : out std_logic_vector(15 downto 0));
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11 | end siggen;
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12 |
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13 | architecture Behavioral of siggen is
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14 |
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15 | signal signalart: integer range 0 to 63:=0;
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16 | signal freq_counter: unsigned(9 downto 0):=(others => '0');
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17 | signal pointer: integer range 0 to 1023:=0;
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18 | signal sin: unsigned(9 downto 0):=(others => '0');
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19 | signal output_buff: std_logic_vector(15 downto 0):=(others => '0');
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20 | type Rom512x9 is array (0 to 511) of unsigned(8 downto 0);
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21 | signal Sinus_Rom : Rom512x9;
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22 |
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23 | begin
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24 |
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25 | tabel : for I in 0 to 511 generate
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26 | Sinus_Rom(I) <= to_unsigned(integer( sin(2.0*MATH_PI*(real(I)+0.5)/1024.0)*511.5),9);
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27 | end generate;
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28 |
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29 | process begin
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30 | wait until rising_edge(clk);
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31 | freq_counter <= freq_counter +1;
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32 | output <= output_buff;
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33 |
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34 | if freq_counter >= unsigned(freq) then
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35 | freq_counter <= (others => '0');
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36 | end if;
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37 |
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38 | if freq_counter = 0 then
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39 | pointer <= pointer +1;
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40 | end if;
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41 |
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42 | if sigtype = "000" then
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43 | if pointer < 512 then
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44 | output_buff <= (others => '0');
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45 | else
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46 | output_buff <= std_logic_vector(to_unsigned(1023*19,16));
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47 | end if;
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48 | elsif sigtype = "001" then
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49 | if pointer < 512 then
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50 | output_buff <= std_logic_vector(to_unsigned(pointer*38,16));
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51 | else
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52 | output_buff <= std_logic_vector(to_unsigned(1023*38 - pointer*38,16));
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53 | end if;
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54 | elsif sigtype = "010" then
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55 | output_buff <= std_logic_vector(to_unsigned(pointer*19,16));
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56 | elsif sigtype = "011" then
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57 | if pointer < 512 then
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58 | sin <= to_unsigned(511 + to_integer(Sinus_Rom(pointer)),10);
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59 | else
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60 | sin <= to_unsigned(511 - to_integer(Sinus_Rom(pointer - 512)),10);
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61 | end if;
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62 | output_buff <= std_logic_vector(to_unsigned(to_integer(sin)*19,16));
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63 | end if;
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64 |
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65 | end process;
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66 |
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67 | end Behavioral;
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Und hier die Testbench dazu, läuft aber nicht die Simulation weil die
Fehler vorher auftreten.
1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 |
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4 | entity siggen_bench is
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5 | end siggen_bench;
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6 |
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7 | architecture Behavioral of siggen_bench is
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8 |
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9 | component siggen is port(
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10 | clk : in std_logic;
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11 | sigtype : in std_logic_vector(12 downto 10);
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12 | freq : in std_logic_vector(9 downto 0);
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13 | output : out std_logic_vector(15 downto 0));
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14 | end component;
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15 |
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16 | signal clk_in: std_logic:='0';
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17 | signal output_out: std_logic_vector(9 downto 0):=(others => '0');
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18 | constant clk_in_half_period : time := 5 ns;
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19 |
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20 | begin
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21 |
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22 | s0: siggen port map(
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23 | clk => clk_in,
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24 | sigtype => "011",
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25 | freq => "0000000001",
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26 | output => output_out);
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27 |
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28 | clk_in <= not clk_in after clk_in_half_period;
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29 |
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30 | end Behavioral;
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