1 | ;***** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ********************
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2 | ;***** Created: 2011-08-25 21:00 ******* Source: ATmega8.xml *************
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3 | ;*************************************************************************
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4 | ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
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5 | ;*
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6 | ;* Number : AVR000
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7 | ;* File Name : "m8def.inc"
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8 | ;* Title : Register/Bit Definitions for the ATmega8
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9 | ;* Date : 2011-08-25
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10 | ;* Version : 2.35
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11 | ;* Support E-mail : avr@atmel.com
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12 | ;* Target MCU : ATmega8
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13 | ;*
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14 | ;* DESCRIPTION
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15 | ;* When including this file in the assembly program file, all I/O register
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16 | ;* names and I/O register bit names appearing in the data book can be used.
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17 | ;* In addition, the six registers forming the three data pointers X, Y and
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18 | ;* Z have been assigned names XL - ZH. Highest RAM address for Internal
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19 | ;* SRAM is also defined
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20 | ;*
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21 | ;* The Register names are represented by their hexadecimal address.
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22 | ;*
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23 | ;* The Register Bit names are represented by their bit number (0-7).
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24 | ;*
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25 | ;* Please observe the difference in using the bit names with instructions
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26 | ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
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27 | ;* (skip if bit in register set/cleared). The following example illustrates
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28 | ;* this:
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29 | ;*
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30 | ;* in r16,PORTB ;read PORTB latch
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31 | ;* sbr r16,(1<<PB6)+(1<<PB5) ;set PB6 and PB5 (use masks, not bit#)
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32 | ;* out PORTB,r16 ;output to PORTB
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33 | ;*
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34 | ;* in r16,TIFR ;read the Timer Interrupt Flag Register
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35 | ;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
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36 | ;* rjmp TOV0_is_set ;jump if set
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37 | ;* ... ;otherwise do something else
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38 | ;*************************************************************************
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39 |
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40 | #ifndef _M8DEF_INC_
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41 | #define _M8DEF_INC_
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42 |
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43 |
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44 | #pragma partinc 0
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45 |
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46 | ; ***** SPECIFY DEVICE ***************************************************
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47 | .device ATmega8
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48 | #pragma AVRPART ADMIN PART_NAME ATmega8
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49 | .equ SIGNATURE_000 = 0x1e
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50 | .equ SIGNATURE_001 = 0x93
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51 | .equ SIGNATURE_002 = 0x07
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52 |
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53 | #pragma AVRPART CORE CORE_VERSION V2E
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54 |
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55 |
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56 | ; ***** I/O REGISTER DEFINITIONS *****************************************
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57 | ; NOTE:
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58 | ; Definitions marked "MEMORY MAPPED"are extended I/O ports
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59 | ; and cannot be used with IN/OUT instructions
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60 | .equ SREG = 0x3f
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61 | .equ SPL = 0x3d
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62 | .equ SPH = 0x3e
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63 | .equ GICR = 0x3b
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64 | .equ GIFR = 0x3a
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65 | .equ TIMSK = 0x39
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66 | .equ TIFR = 0x38
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67 | .equ SPMCR = 0x37
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68 | .equ TWCR = 0x36
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69 | .equ MCUCR = 0x35
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70 | .equ MCUCSR = 0x34
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71 | .equ TCCR0 = 0x33
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72 | .equ TCNT0 = 0x32
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73 | .equ OSCCAL = 0x31
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74 | .equ SFIOR = 0x30
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75 | .equ TCCR1A = 0x2f
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76 | .equ TCCR1B = 0x2e
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77 | .equ TCNT1L = 0x2c
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78 | .equ TCNT1H = 0x2d
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79 | .equ OCR1AL = 0x2a
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80 | .equ OCR1AH = 0x2b
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81 | .equ OCR1BL = 0x28
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82 | .equ OCR1BH = 0x29
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83 | .equ ICR1L = 0x26
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84 | .equ ICR1H = 0x27
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85 | .equ TCCR2 = 0x25
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86 | .equ TCNT2 = 0x24
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87 | .equ OCR2 = 0x23
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88 | .equ ASSR = 0x22
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89 | .equ WDTCR = 0x21
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90 | .equ UBRRH = 0x20
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91 | .equ UCSRC = 0x20
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92 | .equ EEARL = 0x1e
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93 | .equ EEARH = 0x1f
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94 | .equ EEDR = 0x1d
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95 | .equ EECR = 0x1c
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96 | .equ PORTB = 0x18
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97 | .equ DDRB = 0x17
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98 | .equ PINB = 0x16
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99 | .equ PORTC = 0x15
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100 | .equ DDRC = 0x14
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101 | .equ PINC = 0x13
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102 | .equ PORTD = 0x12
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103 | .equ DDRD = 0x11
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104 | .equ PIND = 0x10
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105 | .equ SPDR = 0x0f
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106 | .equ SPSR = 0x0e
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107 | .equ SPCR = 0x0d
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108 | .equ UDR = 0x0c
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109 | .equ UCSRA = 0x0b
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110 | .equ UCSRB = 0x0a
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111 | .equ UBRRL = 0x09
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112 | .equ ACSR = 0x08
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113 | .equ ADMUX = 0x07
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114 | .equ ADCSRA = 0x06
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115 | .equ ADCL = 0x04
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116 | .equ ADCH = 0x05
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117 | .equ TWDR = 0x03
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118 | .equ TWAR = 0x02
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119 | .equ TWSR = 0x01
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120 | .equ TWBR = 0x00
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121 |
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122 |
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123 | ; ***** BIT DEFINITIONS **************************************************
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124 |
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125 | ; ***** ANALOG_COMPARATOR ************
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126 | ; SFIOR - Special Function IO Register
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127 | .equ ACME = 3 ; Analog Comparator Multiplexer Enable
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128 |
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129 | ; ACSR - Analog Comparator Control And Status Register
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130 | .equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
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131 | .equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
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132 | .equ ACIC = 2 ; Analog Comparator Input Capture Enable
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133 | .equ ACIE = 3 ; Analog Comparator Interrupt Enable
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134 | .equ ACI = 4 ; Analog Comparator Interrupt Flag
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135 | .equ ACO = 5 ; Analog Compare Output
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136 | .equ ACBG = 6 ; Analog Comparator Bandgap Select
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137 | .equ ACD = 7 ; Analog Comparator Disable
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138 |
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139 |
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140 | ; ***** SPI **************************
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141 | ; SPDR - SPI Data Register
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142 | .equ SPDR0 = 0 ; SPI Data Register bit 0
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143 | .equ SPDR1 = 1 ; SPI Data Register bit 1
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144 | .equ SPDR2 = 2 ; SPI Data Register bit 2
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145 | .equ SPDR3 = 3 ; SPI Data Register bit 3
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146 | .equ SPDR4 = 4 ; SPI Data Register bit 4
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147 | .equ SPDR5 = 5 ; SPI Data Register bit 5
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148 | .equ SPDR6 = 6 ; SPI Data Register bit 6
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149 | .equ SPDR7 = 7 ; SPI Data Register bit 7
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150 |
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151 | ; SPSR - SPI Status Register
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152 | .equ SPI2X = 0 ; Double SPI Speed Bit
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153 | .equ WCOL = 6 ; Write Collision Flag
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154 | .equ SPIF = 7 ; SPI Interrupt Flag
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155 |
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156 | ; SPCR - SPI Control Register
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157 | .equ SPR0 = 0 ; SPI Clock Rate Select 0
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158 | .equ SPR1 = 1 ; SPI Clock Rate Select 1
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159 | .equ CPHA = 2 ; Clock Phase
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160 | .equ CPOL = 3 ; Clock polarity
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161 | .equ MSTR = 4 ; Master/Slave Select
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162 | .equ DORD = 5 ; Data Order
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163 | .equ SPE = 6 ; SPI Enable
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164 | .equ SPIE = 7 ; SPI Interrupt Enable
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165 |
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166 |
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167 | ; ***** EXTERNAL_INTERRUPT ***********
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168 | ; GICR - General Interrupt Control Register
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169 | .equ GIMSK = GICR ; For compatibility
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170 | .equ IVCE = 0 ; Interrupt Vector Change Enable
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171 | .equ IVSEL = 1 ; Interrupt Vector Select
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172 | .equ INT0 = 6 ; External Interrupt Request 0 Enable
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173 | .equ INT1 = 7 ; External Interrupt Request 1 Enable
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174 |
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175 | ; GIFR - General Interrupt Flag Register
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176 | .equ INTF0 = 6 ; External Interrupt Flag 0
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177 | .equ INTF1 = 7 ; External Interrupt Flag 1
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178 |
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179 | ; MCUCR - MCU Control Register
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180 | .equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0
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181 | .equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1
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182 | .equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0
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183 | .equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1
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184 |
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185 |
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186 | ; ***** TIMER_COUNTER_0 **************
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187 | ; TIMSK - Timer/Counter Interrupt Mask Register
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188 | .equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
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189 |
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190 | ; TIFR - Timer/Counter Interrupt Flag register
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191 | .equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
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192 |
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193 | ; TCCR0 - Timer/Counter0 Control Register
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194 | .equ CS00 = 0 ; Clock Select0 bit 0
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195 | .equ CS01 = 1 ; Clock Select0 bit 1
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196 | .equ CS02 = 2 ; Clock Select0 bit 2
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197 |
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198 | ; TCNT0 - Timer Counter 0
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199 | .equ TCNT00 = 0 ; Timer Counter 0 bit 0
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200 | .equ TCNT01 = 1 ; Timer Counter 0 bit 1
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201 | .equ TCNT02 = 2 ; Timer Counter 0 bit 2
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202 | .equ TCNT03 = 3 ; Timer Counter 0 bit 3
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203 | .equ TCNT04 = 4 ; Timer Counter 0 bit 4
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204 | .equ TCNT05 = 5 ; Timer Counter 0 bit 5
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205 | .equ TCNT06 = 6 ; Timer Counter 0 bit 6
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206 | .equ TCNT07 = 7 ; Timer Counter 0 bit 7
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207 |
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208 |
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209 | ; ***** TIMER_COUNTER_1 **************
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210 | ; TIMSK - Timer/Counter Interrupt Mask Register
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211 | .equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable
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212 | .equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable
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213 | .equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable
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214 | .equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
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215 |
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216 | ; TIFR - Timer/Counter Interrupt Flag register
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217 | .equ TOV1 = 2 ; Timer/Counter1 Overflow Flag
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218 | .equ OCF1B = 3 ; Output Compare Flag 1B
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219 | .equ OCF1A = 4 ; Output Compare Flag 1A
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220 | .equ ICF1 = 5 ; Input Capture Flag 1
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221 |
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222 | ; TCCR1A - Timer/Counter1 Control Register A
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223 | .equ WGM10 = 0 ; Waveform Generation Mode
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224 | .equ PWM10 = WGM10 ; For compatibility
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225 | .equ WGM11 = 1 ; Waveform Generation Mode
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226 | .equ PWM11 = WGM11 ; For compatibility
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227 | .equ FOC1B = 2 ; Force Output Compare 1B
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228 | .equ FOC1A = 3 ; Force Output Compare 1A
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229 | .equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
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230 | .equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
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231 | .equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0
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232 | .equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
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233 |
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234 | ; TCCR1B - Timer/Counter1 Control Register B
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235 | .equ CS10 = 0 ; Prescaler source of Timer/Counter 1
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236 | .equ CS11 = 1 ; Prescaler source of Timer/Counter 1
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237 | .equ CS12 = 2 ; Prescaler source of Timer/Counter 1
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238 | .equ WGM12 = 3 ; Waveform Generation Mode
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239 | .equ CTC10 = WGM12 ; For compatibility
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240 | .equ CTC1 = WGM12 ; For compatibility
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241 | .equ WGM13 = 4 ; Waveform Generation Mode
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242 | .equ CTC11 = WGM13 ; For compatibility
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243 | .equ ICES1 = 6 ; Input Capture 1 Edge Select
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244 | .equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
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245 |
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246 |
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247 | ; ***** TIMER_COUNTER_2 **************
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248 | ; TIMSK - Timer/Counter Interrupt Mask register
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249 | .equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable
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250 | .equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable
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251 |
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252 | ; TIFR - Timer/Counter Interrupt Flag Register
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253 | .equ TOV2 = 6 ; Timer/Counter2 Overflow Flag
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254 | .equ OCF2 = 7 ; Output Compare Flag 2
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255 |
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256 | ; TCCR2 - Timer/Counter2 Control Register
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257 | .equ CS20 = 0 ; Clock Select bit 0
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258 | .equ CS21 = 1 ; Clock Select bit 1
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259 | .equ CS22 = 2 ; Clock Select bit 2
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260 | .equ WGM21 = 3 ; Waveform Generation Mode
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261 | .equ CTC2 = WGM21 ; For compatibility
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262 | .equ COM20 = 4 ; Compare Output Mode bit 0
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263 | .equ COM21 = 5 ; Compare Output Mode bit 1
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264 | .equ WGM20 = 6 ; Waveform Genration Mode
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265 | .equ PWM2 = WGM20 ; For compatibility
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266 | .equ FOC2 = 7 ; Force Output Compare
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267 |
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268 | ; TCNT2 - Timer/Counter2
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269 | .equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0
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270 | .equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1
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271 | .equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2
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272 | .equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3
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273 | .equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4
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274 | .equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5
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275 | .equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6
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276 | .equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7
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277 |
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278 | ; OCR2 - Timer/Counter2 Output Compare Register
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279 | .equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
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280 | .equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
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281 | .equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
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282 | .equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
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283 | .equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
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284 | .equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
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285 | .equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
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286 | .equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
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287 |
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288 | ; ASSR - Asynchronous Status Register
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289 | .equ TCR2UB = 0 ; Timer/counter Control Register2 Update Busy
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290 | .equ OCR2UB = 1 ; Output Compare Register2 Update Busy
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291 | .equ TCN2UB = 2 ; Timer/Counter2 Update Busy
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292 | .equ AS2 = 3 ; Asynchronous Timer/counter2
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293 |
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294 | ; SFIOR - Special Function IO Register
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295 | .equ PSR2 = 1 ; Prescaler Reset Timer/Counter2
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296 |
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297 |
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298 | ; ***** USART ************************
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299 | ; UDR - USART I/O Data Register
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300 | .equ UDR0 = 0 ; USART I/O Data Register bit 0
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301 | .equ UDR1 = 1 ; USART I/O Data Register bit 1
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302 | .equ UDR2 = 2 ; USART I/O Data Register bit 2
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303 | .equ UDR3 = 3 ; USART I/O Data Register bit 3
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304 | .equ UDR4 = 4 ; USART I/O Data Register bit 4
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305 | .equ UDR5 = 5 ; USART I/O Data Register bit 5
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306 | .equ UDR6 = 6 ; USART I/O Data Register bit 6
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307 | .equ UDR7 = 7 ; USART I/O Data Register bit 7
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308 |
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309 | ; UCSRA - USART Control and Status Register A
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310 | .equ USR = UCSRA ; For compatibility
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311 | .equ MPCM = 0 ; Multi-processor Communication Mode
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312 | .equ U2X = 1 ; Double the USART transmission speed
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313 | .equ UPE = 2 ; Parity Error
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314 | .equ PE = UPE ; For compatibility
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315 | .equ DOR = 3 ; Data overRun
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316 | .equ FE = 4 ; Framing Error
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317 | .equ UDRE = 5 ; USART Data Register Empty
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318 | .equ TXC = 6 ; USART Transmitt Complete
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319 | .equ RXC = 7 ; USART Receive Complete
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320 |
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321 | ; UCSRB - USART Control and Status Register B
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322 | .equ UCR = UCSRB ; For compatibility
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323 | .equ TXB8 = 0 ; Transmit Data Bit 8
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324 | .equ RXB8 = 1 ; Receive Data Bit 8
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325 | .equ UCSZ2 = 2 ; Character Size
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326 | .equ CHR9 = UCSZ2 ; For compatibility
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327 | .equ TXEN = 3 ; Transmitter Enable
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328 | .equ RXEN = 4 ; Receiver Enable
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329 | .equ UDRIE = 5 ; USART Data register Empty Interrupt Enable
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330 | .equ TXCIE = 6 ; TX Complete Interrupt Enable
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331 | .equ RXCIE = 7 ; RX Complete Interrupt Enable
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332 |
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333 | ; UCSRC - USART Control and Status Register C
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334 | .equ UCPOL = 0 ; Clock Polarity
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335 | .equ UCSZ0 = 1 ; Character Size
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336 | .equ UCSZ1 = 2 ; Character Size
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337 | .equ USBS = 3 ; Stop Bit Select
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338 | .equ UPM0 = 4 ; Parity Mode Bit 0
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339 | .equ UPM1 = 5 ; Parity Mode Bit 1
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340 | .equ UMSEL = 6 ; USART Mode Select
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341 | .equ URSEL = 7 ; Register Select
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342 |
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343 | .equ UBRRHI = UBRRH ; For compatibility
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344 |
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345 | ; ***** TWI **************************
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346 | ; TWBR - TWI Bit Rate register
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347 | .equ I2BR = TWBR ; For compatibility
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348 | .equ TWBR0 = 0 ;
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349 | .equ TWBR1 = 1 ;
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350 | .equ TWBR2 = 2 ;
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351 | .equ TWBR3 = 3 ;
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352 | .equ TWBR4 = 4 ;
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353 | .equ TWBR5 = 5 ;
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354 | .equ TWBR6 = 6 ;
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355 | .equ TWBR7 = 7 ;
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356 |
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357 | ; TWCR - TWI Control Register
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358 | .equ I2CR = TWCR ; For compatibility
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359 | .equ TWIE = 0 ; TWI Interrupt Enable
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360 | .equ I2IE = TWIE ; For compatibility
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361 | .equ TWEN = 2 ; TWI Enable Bit
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362 | .equ I2EN = TWEN ; For compatibility
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363 | .equ ENI2C = TWEN ; For compatibility
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364 | .equ TWWC = 3 ; TWI Write Collition Flag
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365 | .equ I2WC = TWWC ; For compatibility
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366 | .equ TWSTO = 4 ; TWI Stop Condition Bit
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367 | .equ I2STO = TWSTO ; For compatibility
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368 | .equ TWSTA = 5 ; TWI Start Condition Bit
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369 | .equ I2STA = TWSTA ; For compatibility
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370 | .equ TWEA = 6 ; TWI Enable Acknowledge Bit
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371 | .equ I2EA = TWEA ; For compatibility
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372 | .equ TWINT = 7 ; TWI Interrupt Flag
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373 | .equ I2INT = TWINT ; For compatibility
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374 |
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375 | ; TWSR - TWI Status Register
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376 | .equ I2SR = TWSR ; For compatibility
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377 | .equ TWPS0 = 0 ; TWI Prescaler
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378 | .equ TWS0 = TWPS0 ; For compatibility
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379 | .equ I2GCE = TWPS0 ; For compatibility
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380 | .equ TWPS1 = 1 ; TWI Prescaler
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381 | .equ TWS1 = TWPS1 ; For compatibility
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382 | .equ TWS3 = 3 ; TWI Status
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383 | .equ I2S3 = TWS3 ; For compatibility
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384 | .equ TWS4 = 4 ; TWI Status
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385 | .equ I2S4 = TWS4 ; For compatibility
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386 | .equ TWS5 = 5 ; TWI Status
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387 | .equ I2S5 = TWS5 ; For compatibility
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388 | .equ TWS6 = 6 ; TWI Status
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389 | .equ I2S6 = TWS6 ; For compatibility
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390 | .equ TWS7 = 7 ; TWI Status
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391 | .equ I2S7 = TWS7 ; For compatibility
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392 |
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393 | ; TWDR - TWI Data register
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394 | .equ I2DR = TWDR ; For compatibility
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395 | .equ TWD0 = 0 ; TWI Data Register Bit 0
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396 | .equ TWD1 = 1 ; TWI Data Register Bit 1
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397 | .equ TWD2 = 2 ; TWI Data Register Bit 2
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398 | .equ TWD3 = 3 ; TWI Data Register Bit 3
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399 | .equ TWD4 = 4 ; TWI Data Register Bit 4
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400 | .equ TWD5 = 5 ; TWI Data Register Bit 5
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401 | .equ TWD6 = 6 ; TWI Data Register Bit 6
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402 | .equ TWD7 = 7 ; TWI Data Register Bit 7
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403 |
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404 | ; TWAR - TWI (Slave) Address register
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405 | .equ I2AR = TWAR ; For compatibility
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406 | .equ TWGCE = 0 ; TWI General Call Recognition Enable Bit
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407 | .equ TWA0 = 1 ; TWI (Slave) Address register Bit 0
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408 | .equ TWA1 = 2 ; TWI (Slave) Address register Bit 1
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409 | .equ TWA2 = 3 ; TWI (Slave) Address register Bit 2
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410 | .equ TWA3 = 4 ; TWI (Slave) Address register Bit 3
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411 | .equ TWA4 = 5 ; TWI (Slave) Address register Bit 4
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412 | .equ TWA5 = 6 ; TWI (Slave) Address register Bit 5
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413 | .equ TWA6 = 7 ; TWI (Slave) Address register Bit 6
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414 |
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415 |
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416 | ; ***** WATCHDOG *********************
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417 | ; WDTCR - Watchdog Timer Control Register
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418 | .equ WDTCSR = WDTCR ; For compatibility
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419 | .equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
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420 | .equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
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421 | .equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
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422 | .equ WDE = 3 ; Watch Dog Enable
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423 | .equ WDCE = 4 ; Watchdog Change Enable
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424 | .equ WDTOE = WDCE ; For compatibility
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425 |
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426 |
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427 | ; ***** PORTB ************************
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428 | ; PORTB - Port B Data Register
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429 | .equ PORTB0 = 0 ; Port B Data Register bit 0
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430 | .equ PB0 = 0 ; For compatibility
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431 | .equ PORTB1 = 1 ; Port B Data Register bit 1
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432 | .equ PB1 = 1 ; For compatibility
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433 | .equ PORTB2 = 2 ; Port B Data Register bit 2
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434 | .equ PB2 = 2 ; For compatibility
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435 | .equ PORTB3 = 3 ; Port B Data Register bit 3
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436 | .equ PB3 = 3 ; For compatibility
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437 | .equ PORTB4 = 4 ; Port B Data Register bit 4
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438 | .equ PB4 = 4 ; For compatibility
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439 | .equ PORTB5 = 5 ; Port B Data Register bit 5
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440 | .equ PB5 = 5 ; For compatibility
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441 | .equ PORTB6 = 6 ; Port B Data Register bit 6
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442 | .equ PB6 = 6 ; For compatibility
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443 | .equ PORTB7 = 7 ; Port B Data Register bit 7
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444 | .equ PB7 = 7 ; For compatibility
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445 |
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446 | ; DDRB - Port B Data Direction Register
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447 | .equ DDB0 = 0 ; Port B Data Direction Register bit 0
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448 | .equ DDB1 = 1 ; Port B Data Direction Register bit 1
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449 | .equ DDB2 = 2 ; Port B Data Direction Register bit 2
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450 | .equ DDB3 = 3 ; Port B Data Direction Register bit 3
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451 | .equ DDB4 = 4 ; Port B Data Direction Register bit 4
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452 | .equ DDB5 = 5 ; Port B Data Direction Register bit 5
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453 | .equ DDB6 = 6 ; Port B Data Direction Register bit 6
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454 | .equ DDB7 = 7 ; Port B Data Direction Register bit 7
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455 |
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456 | ; PINB - Port B Input Pins
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457 | .equ PINB0 = 0 ; Port B Input Pins bit 0
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458 | .equ PINB1 = 1 ; Port B Input Pins bit 1
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459 | .equ PINB2 = 2 ; Port B Input Pins bit 2
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460 | .equ PINB3 = 3 ; Port B Input Pins bit 3
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461 | .equ PINB4 = 4 ; Port B Input Pins bit 4
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462 | .equ PINB5 = 5 ; Port B Input Pins bit 5
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463 | .equ PINB6 = 6 ; Port B Input Pins bit 6
|
464 | .equ PINB7 = 7 ; Port B Input Pins bit 7
|
465 |
|
466 |
|
467 | ; ***** PORTC ************************
|
468 | ; PORTC - Port C Data Register
|
469 | .equ PORTC0 = 0 ; Port C Data Register bit 0
|
470 | .equ PC0 = 0 ; For compatibility
|
471 | .equ PORTC1 = 1 ; Port C Data Register bit 1
|
472 | .equ PC1 = 1 ; For compatibility
|
473 | .equ PORTC2 = 2 ; Port C Data Register bit 2
|
474 | .equ PC2 = 2 ; For compatibility
|
475 | .equ PORTC3 = 3 ; Port C Data Register bit 3
|
476 | .equ PC3 = 3 ; For compatibility
|
477 | .equ PORTC4 = 4 ; Port C Data Register bit 4
|
478 | .equ PC4 = 4 ; For compatibility
|
479 | .equ PORTC5 = 5 ; Port C Data Register bit 5
|
480 | .equ PC5 = 5 ; For compatibility
|
481 | .equ PORTC6 = 6 ; Port C Data Register bit 6
|
482 | .equ PC6 = 6 ; For compatibility
|
483 |
|
484 | ; DDRC - Port C Data Direction Register
|
485 | .equ DDC0 = 0 ; Port C Data Direction Register bit 0
|
486 | .equ DDC1 = 1 ; Port C Data Direction Register bit 1
|
487 | .equ DDC2 = 2 ; Port C Data Direction Register bit 2
|
488 | .equ DDC3 = 3 ; Port C Data Direction Register bit 3
|
489 | .equ DDC4 = 4 ; Port C Data Direction Register bit 4
|
490 | .equ DDC5 = 5 ; Port C Data Direction Register bit 5
|
491 | .equ DDC6 = 6 ; Port C Data Direction Register bit 6
|
492 |
|
493 | ; PINC - Port C Input Pins
|
494 | .equ PINC0 = 0 ; Port C Input Pins bit 0
|
495 | .equ PINC1 = 1 ; Port C Input Pins bit 1
|
496 | .equ PINC2 = 2 ; Port C Input Pins bit 2
|
497 | .equ PINC3 = 3 ; Port C Input Pins bit 3
|
498 | .equ PINC4 = 4 ; Port C Input Pins bit 4
|
499 | .equ PINC5 = 5 ; Port C Input Pins bit 5
|
500 | .equ PINC6 = 6 ; Port C Input Pins bit 6
|
501 |
|
502 |
|
503 | ; ***** PORTD ************************
|
504 | ; PORTD - Port D Data Register
|
505 | .equ PORTD0 = 0 ; Port D Data Register bit 0
|
506 | .equ PD0 = 0 ; For compatibility
|
507 | .equ PORTD1 = 1 ; Port D Data Register bit 1
|
508 | .equ PD1 = 1 ; For compatibility
|
509 | .equ PORTD2 = 2 ; Port D Data Register bit 2
|
510 | .equ PD2 = 2 ; For compatibility
|
511 | .equ PORTD3 = 3 ; Port D Data Register bit 3
|
512 | .equ PD3 = 3 ; For compatibility
|
513 | .equ PORTD4 = 4 ; Port D Data Register bit 4
|
514 | .equ PD4 = 4 ; For compatibility
|
515 | .equ PORTD5 = 5 ; Port D Data Register bit 5
|
516 | .equ PD5 = 5 ; For compatibility
|
517 | .equ PORTD6 = 6 ; Port D Data Register bit 6
|
518 | .equ PD6 = 6 ; For compatibility
|
519 | .equ PORTD7 = 7 ; Port D Data Register bit 7
|
520 | .equ PD7 = 7 ; For compatibility
|
521 |
|
522 | ; DDRD - Port D Data Direction Register
|
523 | .equ DDD0 = 0 ; Port D Data Direction Register bit 0
|
524 | .equ DDD1 = 1 ; Port D Data Direction Register bit 1
|
525 | .equ DDD2 = 2 ; Port D Data Direction Register bit 2
|
526 | .equ DDD3 = 3 ; Port D Data Direction Register bit 3
|
527 | .equ DDD4 = 4 ; Port D Data Direction Register bit 4
|
528 | .equ DDD5 = 5 ; Port D Data Direction Register bit 5
|
529 | .equ DDD6 = 6 ; Port D Data Direction Register bit 6
|
530 | .equ DDD7 = 7 ; Port D Data Direction Register bit 7
|
531 |
|
532 | ; PIND - Port D Input Pins
|
533 | .equ PIND0 = 0 ; Port D Input Pins bit 0
|
534 | .equ PIND1 = 1 ; Port D Input Pins bit 1
|
535 | .equ PIND2 = 2 ; Port D Input Pins bit 2
|
536 | .equ PIND3 = 3 ; Port D Input Pins bit 3
|
537 | .equ PIND4 = 4 ; Port D Input Pins bit 4
|
538 | .equ PIND5 = 5 ; Port D Input Pins bit 5
|
539 | .equ PIND6 = 6 ; Port D Input Pins bit 6
|
540 | .equ PIND7 = 7 ; Port D Input Pins bit 7
|
541 |
|
542 |
|
543 | ; ***** EEPROM ***********************
|
544 | ; EEDR - EEPROM Data Register
|
545 | .equ EEDR0 = 0 ; EEPROM Data Register bit 0
|
546 | .equ EEDR1 = 1 ; EEPROM Data Register bit 1
|
547 | .equ EEDR2 = 2 ; EEPROM Data Register bit 2
|
548 | .equ EEDR3 = 3 ; EEPROM Data Register bit 3
|
549 | .equ EEDR4 = 4 ; EEPROM Data Register bit 4
|
550 | .equ EEDR5 = 5 ; EEPROM Data Register bit 5
|
551 | .equ EEDR6 = 6 ; EEPROM Data Register bit 6
|
552 | .equ EEDR7 = 7 ; EEPROM Data Register bit 7
|
553 |
|
554 | ; EECR - EEPROM Control Register
|
555 | .equ EERE = 0 ; EEPROM Read Enable
|
556 | .equ EEWE = 1 ; EEPROM Write Enable
|
557 | .equ EEMWE = 2 ; EEPROM Master Write Enable
|
558 | .equ EEWEE = EEMWE ; For compatibility
|
559 | .equ EERIE = 3 ; EEPROM Ready Interrupt Enable
|
560 |
|
561 |
|
562 | ; ***** CPU **************************
|
563 | ; SREG - Status Register
|
564 | .equ SREG_C = 0 ; Carry Flag
|
565 | .equ SREG_Z = 1 ; Zero Flag
|
566 | .equ SREG_N = 2 ; Negative Flag
|
567 | .equ SREG_V = 3 ; Two's Complement Overflow Flag
|
568 | .equ SREG_S = 4 ; Sign Bit
|
569 | .equ SREG_H = 5 ; Half Carry Flag
|
570 | .equ SREG_T = 6 ; Bit Copy Storage
|
571 | .equ SREG_I = 7 ; Global Interrupt Enable
|
572 |
|
573 | ; MCUCR - MCU Control Register
|
574 | ;.equ ISC00 = 0 ; Interrupt Sense Control 0 Bit 0
|
575 | ;.equ ISC01 = 1 ; Interrupt Sense Control 0 Bit 1
|
576 | ;.equ ISC10 = 2 ; Interrupt Sense Control 1 Bit 0
|
577 | ;.equ ISC11 = 3 ; Interrupt Sense Control 1 Bit 1
|
578 | .equ SM0 = 4 ; Sleep Mode Select
|
579 | .equ SM1 = 5 ; Sleep Mode Select
|
580 | .equ SM2 = 6 ; Sleep Mode Select
|
581 | .equ SE = 7 ; Sleep Enable
|
582 |
|
583 | ; MCUCSR - MCU Control And Status Register
|
584 | .equ MCUSR = MCUCSR ; For compatibility
|
585 | .equ PORF = 0 ; Power-on reset flag
|
586 | .equ EXTRF = 1 ; External Reset Flag
|
587 | .equ BORF = 2 ; Brown-out Reset Flag
|
588 | .equ WDRF = 3 ; Watchdog Reset Flag
|
589 |
|
590 | ; OSCCAL - Oscillator Calibration Value
|
591 | .equ CAL0 = 0 ; Oscillator Calibration Value Bit0
|
592 | .equ CAL1 = 1 ; Oscillator Calibration Value Bit1
|
593 | .equ CAL2 = 2 ; Oscillator Calibration Value Bit2
|
594 | .equ CAL3 = 3 ; Oscillator Calibration Value Bit3
|
595 | .equ CAL4 = 4 ; Oscillator Calibration Value Bit4
|
596 | .equ CAL5 = 5 ; Oscillator Calibration Value Bit5
|
597 | .equ CAL6 = 6 ; Oscillator Calibration Value Bit6
|
598 | .equ CAL7 = 7 ; Oscillator Calibration Value Bit7
|
599 |
|
600 | ; SPMCR - Store Program Memory Control Register
|
601 | .equ SPMEN = 0 ; Store Program Memory Enable
|
602 | .equ PGERS = 1 ; Page Erase
|
603 | .equ PGWRT = 2 ; Page Write
|
604 | .equ BLBSET = 3 ; Boot Lock Bit Set
|
605 | .equ RWWSRE = 4 ; Read-While-Write Section Read Enable
|
606 | .equ RWWSB = 6 ; Read-While-Write Section Busy
|
607 | .equ SPMIE = 7 ; SPM Interrupt Enable
|
608 |
|
609 | ; SFIOR - Special Function IO Register
|
610 | .equ PSR10 = 0 ; Prescaler Reset Timer/Counter1 and Timer/Counter0
|
611 | .equ PUD = 2 ; Pull-up Disable
|
612 | .equ ADHSM = 4 ; ADC High Speed Mode
|
613 |
|
614 |
|
615 | ; ***** AD_CONVERTER *****************
|
616 | ; ADMUX - The ADC multiplexer Selection Register
|
617 | .equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
|
618 | .equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
|
619 | .equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
|
620 | .equ MUX3 = 3 ; Analog Channel and Gain Selection Bits
|
621 | .equ ADLAR = 5 ; Left Adjust Result
|
622 | .equ REFS0 = 6 ; Reference Selection Bit 0
|
623 | .equ REFS1 = 7 ; Reference Selection Bit 1
|
624 |
|
625 | ; ADCSRA - The ADC Control and Status register
|
626 | .equ ADCSR = ADCSRA ; For compatibility
|
627 | .equ ADPS0 = 0 ; ADC Prescaler Select Bits
|
628 | .equ ADPS1 = 1 ; ADC Prescaler Select Bits
|
629 | .equ ADPS2 = 2 ; ADC Prescaler Select Bits
|
630 | .equ ADIE = 3 ; ADC Interrupt Enable
|
631 | .equ ADIF = 4 ; ADC Interrupt Flag
|
632 | .equ ADFR = 5 ; ADC Free Running Select
|
633 | .equ ADSC = 6 ; ADC Start Conversion
|
634 | .equ ADEN = 7 ; ADC Enable
|
635 |
|
636 |
|
637 |
|
638 | ; ***** LOCKSBITS ********************************************************
|
639 | .equ LB1 = 0 ; Lock bit
|
640 | .equ LB2 = 1 ; Lock bit
|
641 | .equ BLB01 = 2 ; Boot Lock bit
|
642 | .equ BLB02 = 3 ; Boot Lock bit
|
643 | .equ BLB11 = 4 ; Boot lock bit
|
644 | .equ BLB12 = 5 ; Boot lock bit
|
645 |
|
646 |
|
647 | ; ***** FUSES ************************************************************
|
648 | ; LOW fuse bits
|
649 | .equ CKSEL0 = 0 ; Select Clock Source
|
650 | .equ CKSEL1 = 1 ; Select Clock Source
|
651 | .equ CKSEL2 = 2 ; Select Clock Source
|
652 | .equ CKSEL3 = 3 ; Select Clock Source
|
653 | .equ SUT0 = 4 ; Select start-up time
|
654 | .equ SUT1 = 5 ; Select start-up time
|
655 | .equ BODEN = 6 ; Brown out detector enable
|
656 | .equ BODLEVEL = 7 ; Brown out detector trigger level
|
657 |
|
658 | ; HIGH fuse bits
|
659 | .equ BOOTRST = 0 ; Select Reset Vector
|
660 | .equ BOOTSZ0 = 1 ; Select Boot Size
|
661 | .equ BOOTSZ1 = 2 ; Select Boot Size
|
662 | .equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
|
663 | .equ CKOPT = 4 ; Oscillator Options
|
664 | .equ SPIEN = 5 ; Enable Serial programming and Data Downloading
|
665 | .equ WTDON = 6 ; Enable watchdog
|
666 | .equ RSTDISBL = 7 ; Disable reset
|
667 |
|
668 |
|
669 |
|
670 | ; ***** CPU REGISTER DEFINITIONS *****************************************
|
671 | .def XH = r27
|
672 | .def XL = r26
|
673 | .def YH = r29
|
674 | .def YL = r28
|
675 | .def ZH = r31
|
676 | .def ZL = r30
|
677 |
|
678 |
|
679 |
|
680 | ; ***** DATA MEMORY DECLARATIONS *****************************************
|
681 | .equ FLASHEND = 0x0fff ; Note: Word address
|
682 | .equ IOEND = 0x003f
|
683 | .equ SRAM_START = 0x0060
|
684 | .equ SRAM_SIZE = 1024
|
685 | .equ RAMEND = 0x045f
|
686 | .equ XRAMEND = 0x0000
|
687 | .equ E2END = 0x01ff
|
688 | .equ EEPROMEND = 0x01ff
|
689 | .equ EEADRBITS = 9
|
690 | #pragma AVRPART MEMORY PROG_FLASH 8192
|
691 | #pragma AVRPART MEMORY EEPROM 512
|
692 | #pragma AVRPART MEMORY INT_SRAM SIZE 1024
|
693 | #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
|
694 |
|
695 |
|
696 |
|
697 | ; ***** BOOTLOADER DECLARATIONS ******************************************
|
698 | .equ NRWW_START_ADDR = 0xc00
|
699 | .equ NRWW_STOP_ADDR = 0xfff
|
700 | .equ RWW_START_ADDR = 0x0
|
701 | .equ RWW_STOP_ADDR = 0xbff
|
702 | .equ PAGESIZE = 32
|
703 | .equ FIRSTBOOTSTART = 0xf80
|
704 | .equ SECONDBOOTSTART = 0xf00
|
705 | .equ THIRDBOOTSTART = 0xe00
|
706 | .equ FOURTHBOOTSTART = 0xc00
|
707 | .equ SMALLBOOTSTART = FIRSTBOOTSTART
|
708 | .equ LARGEBOOTSTART = FOURTHBOOTSTART
|
709 |
|
710 |
|
711 |
|
712 | ; ***** INTERRUPT VECTORS ************************************************
|
713 | .equ INT0addr = 0x0001 ; External Interrupt Request 0
|
714 | .equ INT1addr = 0x0002 ; External Interrupt Request 1
|
715 | .equ OC2addr = 0x0003 ; Timer/Counter2 Compare Match
|
716 | .equ OVF2addr = 0x0004 ; Timer/Counter2 Overflow
|
717 | .equ ICP1addr = 0x0005 ; Timer/Counter1 Capture Event
|
718 | .equ OC1Aaddr = 0x0006 ; Timer/Counter1 Compare Match A
|
719 | .equ OC1Baddr = 0x0007 ; Timer/Counter1 Compare Match B
|
720 | .equ OVF1addr = 0x0008 ; Timer/Counter1 Overflow
|
721 | .equ OVF0addr = 0x0009 ; Timer/Counter0 Overflow
|
722 | .equ SPIaddr = 0x000a ; Serial Transfer Complete
|
723 | .equ URXCaddr = 0x000b ; USART, Rx Complete
|
724 | .equ UDREaddr = 0x000c ; USART Data Register Empty
|
725 | .equ UTXCaddr = 0x000d ; USART, Tx Complete
|
726 | .equ ADCCaddr = 0x000e ; ADC Conversion Complete
|
727 | .equ ERDYaddr = 0x000f ; EEPROM Ready
|
728 | .equ ACIaddr = 0x0010 ; Analog Comparator
|
729 | .equ TWIaddr = 0x0011 ; 2-wire Serial Interface
|
730 | .equ SPMRaddr = 0x0012 ; Store Program Memory Ready
|
731 |
|
732 | .equ INT_VECTORS_SIZE = 19 ; size in words
|
733 |
|
734 | #pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
|
735 |
|
736 | #endif /* _M8DEF_INC_ */
|
737 |
|
738 | ; ***** END OF FILE ******************************************************
|