1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 |
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4 | entity TOP is
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5 | Port (
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6 | CLK : in STD_LOGIC;
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7 |
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8 | TMDSp_clock : out STD_LOGIC;
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9 | TMDSn_clock : out STD_LOGIC
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10 | );
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11 | end TOP;
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12 |
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13 | architecture Behavioral of TOP is
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14 |
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15 | signal RST : STD_LOGIC;
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16 | signal CLK25 : STD_LOGIC;
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17 | signal CLK100 : STD_LOGIC;
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18 |
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19 | component OBUFDS
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20 | generic (
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21 | IOSTANDARD : string := "LVDS_25"
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22 | );
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23 | port (
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24 | I : in STD_LOGIC;
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25 | O : out STD_LOGIC;
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26 | OB : out STD_LOGIC
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27 | );
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28 | end component;
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29 |
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30 | component DCM
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31 | generic (
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32 | DFS_FREQUENCY_MODE : string := "LOW";
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33 | DLL_FREQUENCY_MODE : string := "LOW";
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34 | DUTY_CYCLE_CORRECTION : boolean := TRUE;
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35 | CLKIN_DIVIDE_BY_2 : boolean := FALSE;
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36 | CLK_FEEDBACK : string := "1X";
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37 | CLKOUT_PHASE_SHIFT : string := "NONE";
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38 | DSS_MODE : string := "NONE";
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39 | STARTUP_WAIT : boolean := FALSE;
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40 | PHASE_SHIFT : integer := 0;
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41 | CLKFX_MULTIPLY : integer := 4;
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42 | CLKFX_DIVIDE : integer := 1;
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43 | CLKDV_DIVIDE : real := 2.0;
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44 | CLKIN_PERIOD : real := 41.66666;
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45 | DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
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46 | CLKIN_BUF : boolean := FALSE;
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47 | CLKFB_BUF : boolean := FALSE;
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48 | CLK0_BUF : boolean := FALSE;
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49 | CLK90_BUF : boolean := FALSE;
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50 | CLK180_BUF : boolean := FALSE;
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51 | CLK270_BUF : boolean := FALSE;
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52 | CLKDV_BUF : boolean := FALSE;
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53 | CLK2X_BUF : boolean := FALSE;
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54 | CLK2X180_BUF : boolean := FALSE;
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55 | CLKFX_BUF : boolean := FALSE;
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56 | CLKFX180_BUF : boolean := FALSE;
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57 | EXT_RESET_HIGH : integer := 1
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58 | );
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59 | port (
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60 | CLKIN : in std_logic;
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61 | CLKFB : in std_logic;
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62 | DSSEN : in std_logic;
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63 | PSINCDEC : in std_logic;
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64 | PSEN : in std_logic;
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65 | PSCLK : in std_logic;
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66 | RST : in std_logic;
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67 | CLK0 : out std_logic;
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68 | CLK90 : out std_logic;
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69 | CLK180 : out std_logic;
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70 | CLK270 : out std_logic;
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71 | CLK2X : out std_logic;
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72 | CLK2X180 : out std_logic;
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73 | CLKDV : out std_logic;
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74 | CLKFX : out std_logic;
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75 | CLKFX180 : out std_logic;
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76 | LOCKED : out std_logic;
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77 | PSDONE : out std_logic;
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78 | STATUS : out std_logic_vector(7 downto 0)
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79 | );
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80 | end component;
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81 |
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82 | begin
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83 |
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84 | DCM_inst : DCM
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85 | generic map (
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86 | CLKDV_DIVIDE => 4.0,
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87 | CLKIN_PERIOD => 10.0,
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88 | CLKIN_BUF => TRUE,
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89 | CLK0_BUF => TRUE,
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90 | CLKDV_BUF => TRUE
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91 | )
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92 | port map (
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93 | CLKIN => CLK, -- Clock input (from IBUFG, BUFG or DCM)
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94 | CLKFB => CLK100, -- DCM clock feedback
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95 | DSSEN => '0', -- ?
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96 | PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
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97 | PSEN => '0', -- Dynamic phase adjust enable input
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98 | PSCLK => '0', -- Dynamic phase adjust clock input
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99 | RST => '0', -- DCM asynchronous reset input
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100 | CLK0 => CLK100, -- 0 degree DCM CLK ouptput
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101 | CLK90 => open, -- 90 degree DCM CLK output
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102 | CLK180 => open, -- 180 degree DCM CLK output
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103 | CLK270 => open, -- 270 degree DCM CLK output
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104 | CLK2X => open, -- 2X DCM CLK output
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105 | CLK2X180 => open, -- 2X, 180 degree DCM CLK out
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106 | CLKDV => CLK25, -- Divided DCM CLK out (CLKDV_DIVIDE)
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107 | CLKFX => open, -- DCM CLK synthesis out (M/D)
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108 | CLKFX180 => open, -- 180 degree CLK synthesis out
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109 | LOCKED => open, -- DCM LOCK status output
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110 | PSDONE => open, -- Dynamic phase adjust done output
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111 | STATUS => open -- 8-bit DCM status bits output
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112 | );
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113 |
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114 | OBUFDS_TMDSCLK: OBUFDS
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115 | port map (
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116 | I => CLK25,
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117 | O => TMDSp_clock,
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118 | OB => TMDSn_clock
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119 | );
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120 |
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121 | end Behavioral;
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