1 | /**
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2 | ******************************************************************************
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3 | * @file GPIO/IOToggle/system_stm32f10x.c
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4 | * @author MCD Application Team
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5 | * @version V3.5.0
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6 | * @date 08-April-2011
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7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
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8 | *
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9 | * 1. This file provides two functions and one global variable to be called from
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10 | * user application:
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11 | * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
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12 | * factors, AHB/APBx prescalers and Flash settings).
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13 | * This function is called at startup just after reset and
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14 | * before branch to main program. This call is made inside
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15 | * the "startup_stm32f10x_xx.s" file.
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16 | *
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17 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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18 | * by the user application to setup the SysTick
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19 | * timer or configure other parameters.
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20 | *
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21 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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22 | * be called whenever the core clock is changed
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23 | * during program execution.
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24 | *
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25 | * 2. After each device reset the HSI (8 MHz) is used as system clock source.
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26 | * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
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27 | * configure the system clock before to branch to main program.
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28 | *
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29 | * 3. If the system clock source selected by user fails to startup, the SystemInit()
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30 | * function will do nothing and HSI still used as system clock source. User can
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31 | * add some code to deal with this issue inside the SetSysClock() function.
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32 | *
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33 | * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
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34 | * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
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35 | * When HSE is used as system clock source, directly or through PLL, and you
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36 | * are using different crystal you have to adapt the HSE value to your own
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37 | * configuration.
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38 | *
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39 | ******************************************************************************
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40 | * @attention
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41 | *
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42 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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43 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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44 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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45 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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46 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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47 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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48 | *
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49 | * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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50 | ******************************************************************************
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51 | */
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52 |
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53 | /** @addtogroup CMSIS
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54 | * @{
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55 | */
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56 |
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57 | /** @addtogroup stm32f10x_system
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58 | * @{
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59 | */
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60 |
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61 | /** @addtogroup STM32F10x_System_Private_Includes
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62 | * @{
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63 | */
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64 |
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65 | #include "stm32f10x.h"
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66 |
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67 | /**
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68 | * @}
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69 | */
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70 |
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71 | /** @addtogroup STM32F10x_System_Private_TypesDefinitions
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72 | * @{
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73 | */
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74 |
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75 | /**
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76 | * @}
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77 | */
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78 |
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79 | /** @addtogroup STM32F10x_System_Private_Defines
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80 | * @{
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81 | */
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82 |
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83 | /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
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84 | frequency (after reset the HSI is used as SYSCLK source)
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85 |
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86 | IMPORTANT NOTE:
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87 | ==============
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88 | 1. After each device reset the HSI is used as System clock source.
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89 |
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90 | 2. Please make sure that the selected System clock doesn't exceed your device's
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91 | maximum frequency.
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92 |
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93 | 3. If none of the define below is enabled, the HSI is used as System clock
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94 | source.
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95 |
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96 | 4. The System clock configuration functions provided within this file assume that:
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97 | - For Low, Medium and High density Value line devices an external 8MHz
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98 | crystal is used to drive the System clock.
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99 | - For Low, Medium and High density devices an external 8MHz crystal is
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100 | used to drive the System clock.
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101 | - For Connectivity line devices an external 25MHz crystal is used to drive
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102 | the System clock.
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103 | If you are using different crystal you have to adapt those functions accordingly.
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104 | */
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105 |
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106 |
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107 | // #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL)
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108 | // /* #define SYSCLK_FREQ_HSE HSE_Value */
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109 | // #define SYSCLK_FREQ_24MHz 24000000
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110 | // #else
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111 | // /* #define SYSCLK_FREQ_HSE HSE_Value */
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112 | // #define SYSCLK_FREQ_24MHz 24000000
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113 | // /* #define SYSCLK_FREQ_36MHz 36000000 */
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114 | // /* #define SYSCLK_FREQ_48MHz 48000000 */
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115 | // /* #define SYSCLK_FREQ_56MHz 56000000 */
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116 | // #define SYSCLK_FREQ_72MHz 72000000
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117 | // #endif
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118 |
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119 | #define SYSCLK_FREQ_56MHz 56000000
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120 |
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121 |
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122 | /*!< Uncomment the following line if you need to use external SRAM mounted
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123 | on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
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124 | STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
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125 | #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
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126 | /* #define DATA_IN_ExtSRAM */
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127 | #endif
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128 |
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129 | /*!< Uncomment the following line if you need to relocate your vector Table in
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130 | Internal SRAM. */
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131 | /* #define VECT_TAB_SRAM */
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132 | #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
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133 | This value must be a multiple of 0x200. */
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134 |
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135 |
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136 | /**
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137 | * @}
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138 | */
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139 |
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140 | /** @addtogroup STM32F10x_System_Private_Macros
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141 | * @{
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142 | */
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143 |
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144 | /**
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145 | * @}
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146 | */
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147 |
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148 | /** @addtogroup STM32F10x_System_Private_Variables
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149 | * @{
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150 | */
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151 |
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152 | /*******************************************************************************
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153 | * Clock Definitions
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154 | *******************************************************************************/
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155 | #ifdef SYSCLK_FREQ_HSE
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156 | uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
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157 | #elif defined SYSCLK_FREQ_24MHz
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158 | uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
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159 | #elif defined SYSCLK_FREQ_36MHz
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160 | uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
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161 | #elif defined SYSCLK_FREQ_48MHz
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162 | uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
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163 | #elif defined SYSCLK_FREQ_56MHz
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164 | uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
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165 | #elif defined SYSCLK_FREQ_72MHz
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166 | uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
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167 | #else /*!< HSI Selected as System Clock source */
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168 | uint32_t SystemCoreClock = HSI_Value; /*!< System Clock Frequency (Core Clock) */
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169 | #endif
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170 |
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171 | __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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172 | /**
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173 | * @}
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174 | */
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175 |
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176 | /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
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177 | * @{
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178 | */
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179 |
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180 | static void SetSysClock(void);
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181 |
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182 | #ifdef SYSCLK_FREQ_HSE
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183 | static void SetSysClockToHSE(void);
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184 | #elif defined SYSCLK_FREQ_24MHz
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185 | static void SetSysClockTo24(void);
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186 | #elif defined SYSCLK_FREQ_36MHz
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187 | static void SetSysClockTo36(void);
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188 | #elif defined SYSCLK_FREQ_48MHz
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189 | static void SetSysClockTo48(void);
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190 | #elif defined SYSCLK_FREQ_56MHz
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191 | static void SetSysClockTo56(void);
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192 | #elif defined SYSCLK_FREQ_72MHz
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193 | static void SetSysClockTo72(void);
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194 | #endif
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195 |
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196 | #ifdef DATA_IN_ExtSRAM
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197 | static void SystemInit_ExtMemCtl(void);
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198 | #endif /* DATA_IN_ExtSRAM */
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199 |
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200 | /**
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201 | * @}
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202 | */
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203 |
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204 | /** @addtogroup STM32F10x_System_Private_Functions
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205 | * @{
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206 | */
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207 |
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208 | /**
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209 | * @brief Setup the microcontroller system
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210 | * Initialize the Embedded Flash Interface, the PLL and update the
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211 | * SystemCoreClock variable.
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212 | * @note This function should be used only after reset.
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213 | * @param None
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214 | * @retval None
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215 | */
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216 | void SystemInit (void)
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217 | {
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218 | /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
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219 | /* Set HSION bit */
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220 | RCC->CR |= (uint32_t)0x00000001;
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221 |
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222 | /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
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223 | #ifndef STM32F10X_CL
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224 | RCC->CFGR &= (uint32_t)0xF8FF0000;
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225 | #else
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226 | RCC->CFGR &= (uint32_t)0xF0FF0000;
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227 | #endif /* STM32F10X_CL */
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228 |
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229 | /* Reset HSEON, CSSON and PLLON bits */
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230 | RCC->CR &= (uint32_t)0xFEF6FFFF;
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231 |
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232 | /* Reset HSEBYP bit */
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233 | RCC->CR &= (uint32_t)0xFFFBFFFF;
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234 |
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235 | /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
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236 | RCC->CFGR &= (uint32_t)0xFF80FFFF;
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237 |
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238 | #ifdef STM32F10X_CL
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239 | /* Reset PLL2ON and PLL3ON bits */
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240 | RCC->CR &= (uint32_t)0xEBFFFFFF;
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241 |
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242 | /* Disable all interrupts and clear pending bits */
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243 | RCC->CIR = 0x00FF0000;
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244 |
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245 | /* Reset CFGR2 register */
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246 | RCC->CFGR2 = 0x00000000;
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247 | #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
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248 | /* Disable all interrupts and clear pending bits */
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249 | RCC->CIR = 0x009F0000;
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250 |
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251 | /* Reset CFGR2 register */
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252 | RCC->CFGR2 = 0x00000000;
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253 | #else
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254 | /* Disable all interrupts and clear pending bits */
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255 | RCC->CIR = 0x009F0000;
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256 | #endif /* STM32F10X_CL */
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257 |
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258 | #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
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259 | #ifdef DATA_IN_ExtSRAM
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260 | SystemInit_ExtMemCtl();
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261 | #endif /* DATA_IN_ExtSRAM */
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262 | #endif
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263 |
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264 | /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
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265 | /* Configure the Flash Latency cycles and enable prefetch buffer */
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266 | SetSysClock();
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267 |
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268 | #ifdef VECT_TAB_SRAM
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269 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
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270 | #else
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271 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
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272 | #endif
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273 | }
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274 |
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275 | /**
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276 | * @brief Update SystemCoreClock variable according to Clock Register Values.
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277 | * The SystemCoreClock variable contains the core clock (HCLK), it can
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278 | * be used by the user application to setup the SysTick timer or configure
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279 | * other parameters.
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280 | *
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281 | * @note Each time the core clock (HCLK) changes, this function must be called
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282 | * to update SystemCoreClock variable value. Otherwise, any configuration
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283 | * based on this variable will be incorrect.
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284 | *
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285 | * @note - The system frequency computed by this function is not the real
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286 | * frequency in the chip. It is calculated based on the predefined
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287 | * constant and the selected clock source:
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288 | *
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289 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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290 | *
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291 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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292 | *
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293 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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294 | * or HSI_VALUE(*) multiplied by the PLL factors.
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295 | *
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296 | * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
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297 | * 8 MHz) but the real value may vary depending on the variations
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298 | * in voltage and temperature.
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299 | *
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300 | * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
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301 | * 8 MHz or 25 MHz, depedning on the product used), user has to ensure
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302 | * that HSE_VALUE is same as the real frequency of the crystal used.
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303 | * Otherwise, this function may have wrong result.
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304 | *
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305 | * - The result of this function could be not correct when using fractional
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306 | * value for HSE crystal.
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307 | * @param None
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308 | * @retval None
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309 | */
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310 | void SystemCoreClockUpdate (void)
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311 | {
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312 | uint32_t tmp = 0, pllmull = 0, pllsource = 0;
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313 |
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314 | #ifdef STM32F10X_CL
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315 | uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
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316 | #endif /* STM32F10X_CL */
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317 |
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318 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
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319 | uint32_t prediv1factor = 0;
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320 | #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
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321 |
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322 | /* Get SYSCLK source -------------------------------------------------------*/
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323 | tmp = RCC->CFGR & RCC_CFGR_SWS;
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324 |
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325 | switch (tmp)
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326 | {
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327 | case 0x00: /* HSI used as system clock */
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328 | SystemCoreClock = HSI_VALUE;
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329 | break;
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330 | case 0x04: /* HSE used as system clock */
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331 | SystemCoreClock = HSE_VALUE;
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332 | break;
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333 | case 0x08: /* PLL used as system clock */
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334 |
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335 | /* Get PLL clock source and multiplication factor ----------------------*/
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336 | pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
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337 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
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338 |
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339 | #ifndef STM32F10X_CL
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340 | pllmull = ( pllmull >> 18) + 2;
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341 |
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342 | if (pllsource == 0x00)
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343 | {
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344 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */
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345 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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346 | }
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347 | else
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348 | {
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349 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
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350 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
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351 | /* HSE oscillator clock selected as PREDIV1 clock entry */
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352 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
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353 | #else
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354 | /* HSE selected as PLL clock entry */
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355 | if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
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356 | {/* HSE oscillator clock divided by 2 */
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357 | SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
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358 | }
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359 | else
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360 | {
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361 | SystemCoreClock = HSE_VALUE * pllmull;
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362 | }
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363 | #endif
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364 | }
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365 | #else
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366 | pllmull = pllmull >> 18;
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367 |
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368 | if (pllmull != 0x0D)
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369 | {
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370 | pllmull += 2;
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371 | }
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372 | else
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373 | { /* PLL multiplication factor = PLL input clock * 6.5 */
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374 | pllmull = 13 / 2;
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375 | }
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376 |
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377 | if (pllsource == 0x00)
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378 | {
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379 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */
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380 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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381 | }
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382 | else
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383 | {/* PREDIV1 selected as PLL clock entry */
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384 |
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385 | /* Get PREDIV1 clock source and division factor */
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386 | prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
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387 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
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388 |
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389 | if (prediv1source == 0)
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390 | {
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391 | /* HSE oscillator clock selected as PREDIV1 clock entry */
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392 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
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393 | }
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394 | else
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395 | {/* PLL2 clock selected as PREDIV1 clock entry */
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396 |
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397 | /* Get PREDIV2 division factor and PLL2 multiplication factor */
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398 | prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
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399 | pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
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400 | SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
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401 | }
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402 | }
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403 | #endif /* STM32F10X_CL */
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404 | break;
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405 |
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406 | default:
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407 | SystemCoreClock = HSI_VALUE;
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408 | break;
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409 | }
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410 |
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411 | /* Compute HCLK clock frequency ----------------*/
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412 | /* Get HCLK prescaler */
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413 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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414 | /* HCLK clock frequency */
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415 | SystemCoreClock >>= tmp;
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416 | }
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417 |
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418 | /**
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419 | * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
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420 | * @param None
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421 | * @retval None
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422 | */
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423 | static void SetSysClock(void)
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424 | {
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425 | #ifdef SYSCLK_FREQ_HSE
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426 | SetSysClockToHSE();
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427 | #elif defined SYSCLK_FREQ_24MHz
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428 | SetSysClockTo24();
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429 | #elif defined SYSCLK_FREQ_36MHz
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430 | SetSysClockTo36();
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431 | #elif defined SYSCLK_FREQ_48MHz
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432 | SetSysClockTo48();
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433 | #elif defined SYSCLK_FREQ_56MHz
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434 | SetSysClockTo56();
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435 | #elif defined SYSCLK_FREQ_72MHz
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436 | SetSysClockTo72();
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437 | #endif
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438 |
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439 | /* If none of the define above is enabled, the HSI is used as System clock
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440 | source (default after reset) */
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441 | }
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442 |
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443 | /**
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444 | * @brief Setup the external memory controller. Called in startup_stm32f10x.s
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445 | * before jump to __main
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446 | * @param None
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447 | * @retval None
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448 | */
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449 | #ifdef DATA_IN_ExtSRAM
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450 | /**
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451 | * @brief Setup the external memory controller.
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452 | * Called in startup_stm32f10x_xx.s/.c before jump to main.
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453 | * This function configures the external SRAM mounted on STM3210E-EVAL
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454 | * board (STM32 High density devices). This SRAM will be used as program
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455 | * data memory (including heap and stack).
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456 | * @param None
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457 | * @retval None
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458 | */
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459 | void SystemInit_ExtMemCtl(void)
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460 | {
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461 | /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
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462 | required, then adjust the Register Addresses */
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463 |
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464 | /* Enable FSMC clock */
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465 | RCC->AHBENR = 0x00000114;
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466 |
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467 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
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468 | RCC->APB2ENR = 0x000001E0;
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469 |
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470 | /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
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471 | /*---------------- SRAM Address lines configuration -------------------------*/
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472 | /*---------------- NOE and NWE configuration --------------------------------*/
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473 | /*---------------- NE3 configuration ----------------------------------------*/
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474 | /*---------------- NBL0, NBL1 configuration ---------------------------------*/
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475 |
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476 | GPIOD->CRL = 0x44BB44BB;
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477 | GPIOD->CRH = 0xBBBBBBBB;
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478 |
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479 | GPIOE->CRL = 0xB44444BB;
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480 | GPIOE->CRH = 0xBBBBBBBB;
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481 |
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482 | GPIOF->CRL = 0x44BBBBBB;
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483 | GPIOF->CRH = 0xBBBB4444;
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484 |
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485 | GPIOG->CRL = 0x44BBBBBB;
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486 | GPIOG->CRH = 0x44444B44;
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487 |
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488 | /*---------------- FSMC Configuration ---------------------------------------*/
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489 | /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
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490 |
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491 | FSMC_Bank1->BTCR[4] = 0x00001011;
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492 | FSMC_Bank1->BTCR[5] = 0x00000200;
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493 | }
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494 | #endif /* DATA_IN_ExtSRAM */
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495 |
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496 | #ifdef SYSCLK_FREQ_HSE
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497 | /**
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498 | * @brief Selects HSE as System clock source and configure HCLK, PCLK2
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499 | * and PCLK1 prescalers.
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500 | * @note This function should be used only after reset.
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501 | * @param None
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502 | * @retval None
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503 | */
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504 | static void SetSysClockToHSE(void)
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505 | {
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506 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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507 |
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508 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
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509 | /* Enable HSE */
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510 | RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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511 |
|
512 | /* Wait till HSE is ready and if Time out is reached exit */
|
513 | do
|
514 | {
|
515 | HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
516 | StartUpCounter++;
|
517 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
518 |
|
519 | if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
520 | {
|
521 | HSEStatus = (uint32_t)0x01;
|
522 | }
|
523 | else
|
524 | {
|
525 | HSEStatus = (uint32_t)0x00;
|
526 | }
|
527 |
|
528 | if (HSEStatus == (uint32_t)0x01)
|
529 | {
|
530 |
|
531 | #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
|
532 | /* Enable Prefetch Buffer */
|
533 | FLASH->ACR |= FLASH_ACR_PRFTBE;
|
534 |
|
535 | /* Flash 0 wait state */
|
536 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
|
537 |
|
538 | #ifndef STM32F10X_CL
|
539 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
|
540 | #else
|
541 | if (HSE_VALUE <= 24000000)
|
542 | {
|
543 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
|
544 | }
|
545 | else
|
546 | {
|
547 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
|
548 | }
|
549 | #endif /* STM32F10X_CL */
|
550 | #endif
|
551 |
|
552 | /* HCLK = SYSCLK */
|
553 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
554 |
|
555 | /* PCLK2 = HCLK */
|
556 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
557 |
|
558 | /* PCLK1 = HCLK */
|
559 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
|
560 |
|
561 | /* Select HSE as system clock source */
|
562 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
563 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
|
564 |
|
565 | /* Wait till HSE is used as system clock source */
|
566 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
|
567 | {
|
568 | }
|
569 | }
|
570 | else
|
571 | { /* If HSE fails to start-up, the application will have wrong clock
|
572 | configuration. User can add here some code to deal with this error */
|
573 | }
|
574 | }
|
575 | #elif defined SYSCLK_FREQ_24MHz
|
576 | /**
|
577 | * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
|
578 | * and PCLK1 prescalers.
|
579 | * @note This function should be used only after reset.
|
580 | * @param None
|
581 | * @retval None
|
582 | */
|
583 | static void SetSysClockTo24(void)
|
584 | {
|
585 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
586 |
|
587 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
588 | /* Enable HSE */
|
589 | RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
590 |
|
591 | /* Wait till HSE is ready and if Time out is reached exit */
|
592 | do
|
593 | {
|
594 | HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
595 | StartUpCounter++;
|
596 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
597 |
|
598 | if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
599 | {
|
600 | HSEStatus = (uint32_t)0x01;
|
601 | }
|
602 | else
|
603 | {
|
604 | HSEStatus = (uint32_t)0x00;
|
605 | }
|
606 |
|
607 | if (HSEStatus == (uint32_t)0x01)
|
608 | {
|
609 | #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
|
610 | /* Enable Prefetch Buffer */
|
611 | FLASH->ACR |= FLASH_ACR_PRFTBE;
|
612 |
|
613 | /* Flash 0 wait state */
|
614 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
|
615 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
|
616 | #endif
|
617 |
|
618 | /* HCLK = SYSCLK */
|
619 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
620 |
|
621 | /* PCLK2 = HCLK */
|
622 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
623 |
|
624 | /* PCLK1 = HCLK */
|
625 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
|
626 |
|
627 | #ifdef STM32F10X_CL
|
628 | /* Configure PLLs ------------------------------------------------------*/
|
629 | /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
|
630 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
|
631 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
|
632 | RCC_CFGR_PLLMULL6);
|
633 |
|
634 | /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
635 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
|
636 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
|
637 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
|
638 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
|
639 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
|
640 |
|
641 | /* Enable PLL2 */
|
642 | RCC->CR |= RCC_CR_PLL2ON;
|
643 | /* Wait till PLL2 is ready */
|
644 | while((RCC->CR & RCC_CR_PLL2RDY) == 0)
|
645 | {
|
646 | }
|
647 | #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
|
648 | /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
|
649 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
650 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
|
651 | #else
|
652 | /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
|
653 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
654 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
|
655 | #endif /* STM32F10X_CL */
|
656 |
|
657 | /* Enable PLL */
|
658 | RCC->CR |= RCC_CR_PLLON;
|
659 |
|
660 | /* Wait till PLL is ready */
|
661 | while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
662 | {
|
663 | }
|
664 |
|
665 | /* Select PLL as system clock source */
|
666 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
667 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
668 |
|
669 | /* Wait till PLL is used as system clock source */
|
670 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
|
671 | {
|
672 | }
|
673 | }
|
674 | else
|
675 | { /* If HSE fails to start-up, the application will have wrong clock
|
676 | configuration. User can add here some code to deal with this error */
|
677 | }
|
678 | }
|
679 | #elif defined SYSCLK_FREQ_36MHz
|
680 | /**
|
681 | * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
|
682 | * and PCLK1 prescalers.
|
683 | * @note This function should be used only after reset.
|
684 | * @param None
|
685 | * @retval None
|
686 | */
|
687 | static void SetSysClockTo36(void)
|
688 | {
|
689 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
690 |
|
691 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
692 | /* Enable HSE */
|
693 | RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
694 |
|
695 | /* Wait till HSE is ready and if Time out is reached exit */
|
696 | do
|
697 | {
|
698 | HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
699 | StartUpCounter++;
|
700 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
701 |
|
702 | if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
703 | {
|
704 | HSEStatus = (uint32_t)0x01;
|
705 | }
|
706 | else
|
707 | {
|
708 | HSEStatus = (uint32_t)0x00;
|
709 | }
|
710 |
|
711 | if (HSEStatus == (uint32_t)0x01)
|
712 | {
|
713 | /* Enable Prefetch Buffer */
|
714 | FLASH->ACR |= FLASH_ACR_PRFTBE;
|
715 |
|
716 | /* Flash 1 wait state */
|
717 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
|
718 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
|
719 |
|
720 | /* HCLK = SYSCLK */
|
721 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
722 |
|
723 | /* PCLK2 = HCLK */
|
724 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
725 |
|
726 | /* PCLK1 = HCLK */
|
727 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
|
728 |
|
729 | #ifdef STM32F10X_CL
|
730 | /* Configure PLLs ------------------------------------------------------*/
|
731 |
|
732 | /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
|
733 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
|
734 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
|
735 | RCC_CFGR_PLLMULL9);
|
736 |
|
737 | /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
738 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
|
739 |
|
740 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
|
741 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
|
742 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
|
743 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
|
744 |
|
745 | /* Enable PLL2 */
|
746 | RCC->CR |= RCC_CR_PLL2ON;
|
747 | /* Wait till PLL2 is ready */
|
748 | while((RCC->CR & RCC_CR_PLL2RDY) == 0)
|
749 | {
|
750 | }
|
751 |
|
752 | #else
|
753 | /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
|
754 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
755 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
|
756 | #endif /* STM32F10X_CL */
|
757 |
|
758 | /* Enable PLL */
|
759 | RCC->CR |= RCC_CR_PLLON;
|
760 |
|
761 | /* Wait till PLL is ready */
|
762 | while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
763 | {
|
764 | }
|
765 |
|
766 | /* Select PLL as system clock source */
|
767 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
768 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
769 |
|
770 | /* Wait till PLL is used as system clock source */
|
771 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
|
772 | {
|
773 | }
|
774 | }
|
775 | else
|
776 | { /* If HSE fails to start-up, the application will have wrong clock
|
777 | configuration. User can add here some code to deal with this error */
|
778 | }
|
779 | }
|
780 | #elif defined SYSCLK_FREQ_48MHz
|
781 | /**
|
782 | * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
|
783 | * and PCLK1 prescalers.
|
784 | * @note This function should be used only after reset.
|
785 | * @param None
|
786 | * @retval None
|
787 | */
|
788 | static void SetSysClockTo48(void)
|
789 | {
|
790 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
791 |
|
792 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
793 | /* Enable HSE */
|
794 | RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
795 |
|
796 | /* Wait till HSE is ready and if Time out is reached exit */
|
797 | do
|
798 | {
|
799 | HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
800 | StartUpCounter++;
|
801 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
802 |
|
803 | if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
804 | {
|
805 | HSEStatus = (uint32_t)0x01;
|
806 | }
|
807 | else
|
808 | {
|
809 | HSEStatus = (uint32_t)0x00;
|
810 | }
|
811 |
|
812 | if (HSEStatus == (uint32_t)0x01)
|
813 | {
|
814 | /* Enable Prefetch Buffer */
|
815 | FLASH->ACR |= FLASH_ACR_PRFTBE;
|
816 |
|
817 | /* Flash 1 wait state */
|
818 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
|
819 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
|
820 |
|
821 | /* HCLK = SYSCLK */
|
822 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
823 |
|
824 | /* PCLK2 = HCLK */
|
825 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
826 |
|
827 | /* PCLK1 = HCLK */
|
828 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
|
829 |
|
830 | #ifdef STM32F10X_CL
|
831 | /* Configure PLLs ------------------------------------------------------*/
|
832 | /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
833 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
|
834 |
|
835 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
|
836 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
|
837 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
|
838 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
|
839 |
|
840 | /* Enable PLL2 */
|
841 | RCC->CR |= RCC_CR_PLL2ON;
|
842 | /* Wait till PLL2 is ready */
|
843 | while((RCC->CR & RCC_CR_PLL2RDY) == 0)
|
844 | {
|
845 | }
|
846 |
|
847 |
|
848 | /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
|
849 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
|
850 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
|
851 | RCC_CFGR_PLLMULL6);
|
852 | #else
|
853 | /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
|
854 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
855 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
|
856 | #endif /* STM32F10X_CL */
|
857 |
|
858 | /* Enable PLL */
|
859 | RCC->CR |= RCC_CR_PLLON;
|
860 |
|
861 | /* Wait till PLL is ready */
|
862 | while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
863 | {
|
864 | }
|
865 |
|
866 | /* Select PLL as system clock source */
|
867 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
868 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
869 |
|
870 | /* Wait till PLL is used as system clock source */
|
871 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
|
872 | {
|
873 | }
|
874 | }
|
875 | else
|
876 | { /* If HSE fails to start-up, the application will have wrong clock
|
877 | configuration. User can add here some code to deal with this error */
|
878 | }
|
879 | }
|
880 |
|
881 | #elif defined SYSCLK_FREQ_56MHz
|
882 | /**
|
883 | * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
|
884 | * and PCLK1 prescalers.
|
885 | * @note This function should be used only after reset.
|
886 | * @param None
|
887 | * @retval None
|
888 | */
|
889 | static void SetSysClockTo56(void)
|
890 | {
|
891 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
892 |
|
893 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
894 | /* Enable HSE */
|
895 | RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
896 |
|
897 | /* Wait till HSE is ready and if Time out is reached exit */
|
898 | do
|
899 | {
|
900 | HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
901 | StartUpCounter++;
|
902 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
903 |
|
904 | if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
905 | {
|
906 | HSEStatus = (uint32_t)0x01;
|
907 | }
|
908 | else
|
909 | {
|
910 | HSEStatus = (uint32_t)0x00;
|
911 | }
|
912 |
|
913 | if (HSEStatus == (uint32_t)0x01)
|
914 | {
|
915 | /* Enable Prefetch Buffer */
|
916 | FLASH->ACR |= FLASH_ACR_PRFTBE;
|
917 |
|
918 | /* Flash 2 wait state */
|
919 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
|
920 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
|
921 |
|
922 | /* HCLK = SYSCLK */
|
923 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
924 |
|
925 | /* PCLK2 = HCLK */
|
926 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
927 |
|
928 | /* PCLK1 = HCLK */
|
929 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
|
930 |
|
931 | #ifdef STM32F10X_CL
|
932 | /* Configure PLLs ------------------------------------------------------*/
|
933 | /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
934 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
|
935 |
|
936 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
|
937 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
|
938 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
|
939 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
|
940 |
|
941 | /* Enable PLL2 */
|
942 | RCC->CR |= RCC_CR_PLL2ON;
|
943 | /* Wait till PLL2 is ready */
|
944 | while((RCC->CR & RCC_CR_PLL2RDY) == 0)
|
945 | {
|
946 | }
|
947 |
|
948 |
|
949 | /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
|
950 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
|
951 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
|
952 | RCC_CFGR_PLLMULL7);
|
953 | #else
|
954 | /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
|
955 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
|
956 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
|
957 |
|
958 | #endif /* STM32F10X_CL */
|
959 |
|
960 | /* Enable PLL */
|
961 | RCC->CR |= RCC_CR_PLLON;
|
962 |
|
963 | /* Wait till PLL is ready */
|
964 | while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
965 | {
|
966 | }
|
967 |
|
968 | /* Select PLL as system clock source */
|
969 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
970 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
971 |
|
972 | /* Wait till PLL is used as system clock source */
|
973 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
|
974 | {
|
975 | }
|
976 | }
|
977 | else
|
978 | { /* If HSE fails to start-up, the application will have wrong clock
|
979 | configuration. User can add here some code to deal with this error */
|
980 | }
|
981 | }
|
982 |
|
983 | #elif defined SYSCLK_FREQ_72MHz
|
984 | /**
|
985 | * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
|
986 | * and PCLK1 prescalers.
|
987 | * @note This function should be used only after reset.
|
988 | * @param None
|
989 | * @retval None
|
990 | */
|
991 | static void SetSysClockTo72(void)
|
992 | {
|
993 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
994 |
|
995 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
996 | /* Enable HSE */
|
997 | RCC->CR |= ((uint32_t)RCC_CR_HSEON);
|
998 |
|
999 | /* Wait till HSE is ready and if Time out is reached exit */
|
1000 | do
|
1001 | {
|
1002 | HSEStatus = RCC->CR & RCC_CR_HSERDY;
|
1003 | StartUpCounter++;
|
1004 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
1005 |
|
1006 | if ((RCC->CR & RCC_CR_HSERDY) != RESET)
|
1007 | {
|
1008 | HSEStatus = (uint32_t)0x01;
|
1009 | }
|
1010 | else
|
1011 | {
|
1012 | HSEStatus = (uint32_t)0x00;
|
1013 | }
|
1014 |
|
1015 | if (HSEStatus == (uint32_t)0x01)
|
1016 | {
|
1017 | /* Enable Prefetch Buffer */
|
1018 | FLASH->ACR |= FLASH_ACR_PRFTBE;
|
1019 |
|
1020 | /* Flash 2 wait state */
|
1021 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
|
1022 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
|
1023 |
|
1024 |
|
1025 | /* HCLK = SYSCLK */
|
1026 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
1027 |
|
1028 | /* PCLK2 = HCLK */
|
1029 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
1030 |
|
1031 | /* PCLK1 = HCLK */
|
1032 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
|
1033 |
|
1034 | #ifdef STM32F10X_CL
|
1035 | /* Configure PLLs ------------------------------------------------------*/
|
1036 | /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
|
1037 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
|
1038 |
|
1039 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
|
1040 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
|
1041 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
|
1042 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
|
1043 |
|
1044 | /* Enable PLL2 */
|
1045 | RCC->CR |= RCC_CR_PLL2ON;
|
1046 | /* Wait till PLL2 is ready */
|
1047 | while((RCC->CR & RCC_CR_PLL2RDY) == 0)
|
1048 | {
|
1049 | }
|
1050 |
|
1051 |
|
1052 | /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
|
1053 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
|
1054 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
|
1055 | RCC_CFGR_PLLMULL9);
|
1056 | #else
|
1057 | /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
|
1058 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
|
1059 | RCC_CFGR_PLLMULL));
|
1060 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
|
1061 | #endif /* STM32F10X_CL */
|
1062 |
|
1063 | /* Enable PLL */
|
1064 | RCC->CR |= RCC_CR_PLLON;
|
1065 |
|
1066 | /* Wait till PLL is ready */
|
1067 | while((RCC->CR & RCC_CR_PLLRDY) == 0)
|
1068 | {
|
1069 | }
|
1070 |
|
1071 | /* Select PLL as system clock source */
|
1072 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
1073 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
|
1074 |
|
1075 | /* Wait till PLL is used as system clock source */
|
1076 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
|
1077 | {
|
1078 | }
|
1079 | }
|
1080 | else
|
1081 | { /* If HSE fails to start-up, the application will have wrong clock
|
1082 | configuration. User can add here some code to deal with this error */
|
1083 | }
|
1084 | }
|
1085 | #endif
|
1086 |
|
1087 | /**
|
1088 | * @}
|
1089 | */
|
1090 |
|
1091 | /**
|
1092 | * @}
|
1093 | */
|
1094 |
|
1095 | /**
|
1096 | * @}
|
1097 | */
|
1098 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|