1 | #define CPU_SPEED 32000000UL
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2 | #define BAUDRATE 100000UL
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3 | #define TWI_BAUD(F_SYS, F_TWI) ((F_SYS / (2 * F_TWI)) - 5)
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4 | #define TWI_BAUDSETTING TWI_BAUD(CPU_SPEED, BAUDRATE)
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5 |
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6 |
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7 | void twi_init(TWI_t * twiname){
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8 |
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9 | PORTC.PIN0CTRL = PORT_OPC_WIREDAND_gc;
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10 | PORTC.PIN1CTRL = PORT_OPC_WIREDAND_gc;
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11 | twiname->MASTER.CTRLB = TWI_MASTER_SMEN_bm;
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12 | twiname->MASTER.BAUD = TWI_BAUDSETTING;
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13 | twiname->MASTER.CTRLA = TWI_MASTER_ENABLE_bm;
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14 | twiname->MASTER.STATUS = TWI_MASTER_BUSSTATE_IDLE_gc;
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15 | }
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16 |
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17 | void twi_write(TWI_t *twiname, uint8_t *writeData,uint8_t Adress, uint8_t bytes,bool fixed){
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18 |
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19 | uint8_t i;
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20 | uint8_t address = 0xD0;
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21 | TWIC_MASTER_CTRLC &= ~((1<<TWI_MASTER_ACKACT_bp));
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22 | twiname->MASTER.ADDR = 0xD0;
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23 | while (!(TWIC.MASTER.STATUS & TWI_MASTER_WIF_bm));
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24 | if(TWIC_MASTER_STATUS & (1<<TWI_MASTER_ARBLOST_bp))
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25 | {
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26 | twiname->MASTER.CTRLA = 0;
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27 | PORTC.DIRSET = PIN1_bm;
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28 | for(uint8_t i=0;i<9;i++)
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29 | {
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30 | PORTC.OUTSET = PIN1_bm;
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31 | _delay_us(20);
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32 | PORTC.OUTCLR = PIN1_bm;
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33 | _delay_us(20);
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34 | }
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35 | PORTC.DIRCLR = PIN1_bm;
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36 | twiname->MASTER.CTRLA = TWI_MASTER_ENABLE_bm;
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37 | twiname->MASTER.STATUS = TWI_MASTER_ARBLOST_bm | TWI_MASTER_BUSERR_bm;
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38 | twiname->MASTER.STATUS = TWI_MASTER_BUSSTATE_IDLE_gc;
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39 | TWIC.MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc;
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40 | twiname->MASTER.ADDR = 0xD0;
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41 | if(TWIC_MASTER_STATUS & (1<<TWI_MASTER_ARBLOST_bp));
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42 |
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43 | }
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44 | twiname->MASTER.DATA = Adress; // write word addr
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45 | while(!(twiname->MASTER.STATUS&TWI_MASTER_WIF_bm));
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46 | for(i=0;i<bytes;i++){
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47 | if(!fixed) // write date and time
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48 | twiname->MASTER.DATA =writeData[i];
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49 | else
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50 | twiname->MASTER.DATA =writeData[0];
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51 | while(!(twiname->MASTER.STATUS&TWI_MASTER_WIF_bm));
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52 | }
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53 | TWIC.MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc;
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54 | }
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55 |
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56 | void twi_read(TWI_t *twiname, uint8_t *readData, uint8_t Adress, uint8_t bytes){
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57 | uint8_t address = 0xD0;
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58 | address |= 0x01;
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59 | TWIC_MASTER_CTRLC &= ~((1<<TWI_MASTER_ACKACT_bp));
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60 | twiname->MASTER.ADDR = 0xD0;
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61 | while (!(TWIC.MASTER.STATUS & TWI_MASTER_WIF_bm));
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62 | if(TWIC_MASTER_STATUS & (1<<TWI_MASTER_ARBLOST_bp))
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63 | {
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64 | twiname->MASTER.CTRLA = 0;
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65 | PORTC.DIRSET = PIN1_bm;
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66 | for(uint8_t i=0;i<9;i++)
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67 | {
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68 | PORTC.OUTSET = PIN1_bm;
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69 | _delay_us(20);
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70 | PORTC.OUTCLR = PIN1_bm;
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71 | _delay_us(20);
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72 | }
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73 | PORTC.DIRCLR = PIN1_bm;
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74 | twiname->MASTER.CTRLA = TWI_MASTER_ENABLE_bm;
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75 | twiname->MASTER.STATUS = TWI_MASTER_ARBLOST_bm | TWI_MASTER_BUSERR_bm;
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76 | twiname->MASTER.STATUS = TWI_MASTER_BUSSTATE_IDLE_gc;
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77 | TWIC.MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc;
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78 | twiname->MASTER.ADDR = 0xD0;
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79 | while (!(TWIC.MASTER.STATUS & TWI_MASTER_WIF_bm));
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80 |
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81 | }
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82 | TWIC.MASTER.DATA = Adress;
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83 | while (!(TWIC.MASTER.STATUS & TWI_MASTER_WIF_bm));
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84 | twiname->MASTER.ADDR = 0xD1;
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85 | for(volatile uint8_t j=0 ;j<bytes ;j++){
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86 |
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87 | while(!(twiname->MASTER.STATUS&TWI_MASTER_RIF_bm));
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88 | if(j == (bytes-1))
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89 | {
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90 | TWIC_MASTER_CTRLC = (1<<TWI_MASTER_ACKACT_bp) | TWI_MASTER_CMD_STOP_gc;
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91 | }
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92 | readData[j] = twiname->MASTER.DATA;
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93 | }
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94 | //_delay_us(100);
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95 | //TWIC.MASTER.CTRLC = TWI_MASTER_CMD_STOP_gc;
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96 |
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97 |
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98 |
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99 |
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100 |
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101 | }
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