1 | /*
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2 | This program is free software: you can redistribute it and/or modify
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3 | it under the terms of the GNU General Public License as published by
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4 | the Free Software Foundation, either version 3 of the License, or
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5 | (at your option) any later version.
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6 |
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7 | This program is distributed in the hope that it will be useful,
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8 | but WITHOUT ANY WARRANTY; without even the implied warranty of
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9 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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10 | GNU General Public License for more details.
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11 |
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12 | You should have received a copy of the GNU General Public License
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13 | along with this program. If not, see <http://www.gnu.org/licenses/>.
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14 | *
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15 | * @ Project : MultiSensor
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16 | * @ File Name :SBUS_usart.cpp
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17 | * @ Date : 6/12/2013
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18 | * @ Author : Bart Keser
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19 | *
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20 | */
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21 |
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22 | #include <avr/io.h>
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23 | #include <avr/interrupt.h>
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24 | #include <stdarg.h>
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25 | #include <stdlib.h>
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26 | #include <string.h>
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27 |
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28 | #include "myavr.h"
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29 | #include "SBUS_usart.h"
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30 | #include "usart.h"
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31 |
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32 |
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33 | #define F_CPU 8000000
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34 |
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35 | #define SLOT_DATA_LENGTH 3
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36 | #define NUMBER_OF_FRAMES 4
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37 | #define NUMBER_OF_SLOT 32
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38 | #define NUMBER_OF_SLOT_IN_FRAME 8
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39 | #define SBUS_FRAME_SIZE 25
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40 | #define SBUS_CHANNEL_SIZE 11
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41 |
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42 |
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43 | #define UART_RXBUFSIZE 30
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44 | #define FRAME_TIME_OUT 200 //ms
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45 |
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46 |
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47 | #define TRANSMIT_PIN PIN_0 // digital IO C
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48 | #define RECEIVE_PIN PIN_5 // digital IO B
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49 | #define TRANSMIT_RECEIVE_ENABLE LOW
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50 | #define TRANSMIT_RECEIVE_DISABLE HIGH
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51 |
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52 | #define SLOT_TIME 90 //165
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53 | #define SLOT_TIME2 165
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54 |
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55 |
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56 | uint8_t swaps_slot_bits[8] = {0,4,2,6,1,5,3,7};
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57 |
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58 | uint8_t toggle = 0;
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59 |
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60 |
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61 | //static bool command_received = false;
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62 | //static uint8_t command[UART_RXBUFSIZE];
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63 | //static uint8_t command_length = 9;
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64 |
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65 | // 248 is around 1 ms
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66 | uint8_t transmit_sequence_timer[15] = {250,250,SLOT_TIME2,SLOT_TIME,SLOT_TIME,SLOT_TIME,SLOT_TIME,SLOT_TIME,SLOT_TIME,SLOT_TIME,226,226,226,226,180};
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67 | uint8_t receive_timeout_timer = ( uint8_t ) (248.0 * (FRAME_TIME_OUT / 1000.0));
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68 | uint16_t overflow_counter = 0; // should not occur
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69 |
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70 | static volatile uint8_t rxbuf[UART_RXBUFSIZE];
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71 | static volatile bool frame_ready = false;
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72 | static volatile uint8_t gl_current_frame = 0;
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73 | static volatile uint16_t uart_lost_frame = 0;
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74 |
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75 | typedef enum
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76 | {
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77 | EMPTY = 0,
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78 | TRANSMITTING,
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79 | AVAILABLE
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80 | } SLOT_DATA_STATUS;
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81 |
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82 | typedef struct
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83 | {
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84 | volatile bool data_status;
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85 | volatile uint8_t data[SLOT_DATA_LENGTH];
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86 | } SLOT_RAW_DATA;
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87 |
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88 | // low resolution timer
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89 | volatile uint8_t frameLength = 15;
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90 | volatile int8_t previousFrame = 0;
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91 | volatile uint32_t frameCounter = 0;
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92 |
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93 |
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94 | volatile uint8_t tx_data_counter;
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95 | volatile uint8_t buffer_index;
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96 |
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97 | volatile SLOT_DATA_STATUS transmit_data_per_slot_status[NUMBER_OF_SLOT];
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98 | volatile uint8_t transmit_data_per_slot_data[NUMBER_OF_SLOT][SLOT_DATA_LENGTH];
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99 | volatile uint8_t gl_slot;
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100 |
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101 | void sbus_uart_init();
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102 | void sbus_timer_init();
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103 | void start_receiving();
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104 | void enable_receiving();
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105 | void enable_transmiting();
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106 | void disable_receiving();
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107 | void disable_transmiting();
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108 | void start_transmit_sequencer(uint8_t frame_number);
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109 | void sbus2_send_slot(uint8_t slot);
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110 |
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111 | void ISR_receive_timeout();
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112 | void ISR_transmit();
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113 |
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114 | volatile void (*do_servo_pulls)(uint32_t counter);
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115 |
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116 | volatile void (*timer_ISR)();
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117 |
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118 | //*****************************************************************************
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119 | //
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120 | void SBUS2_uart_setup (void (*start_pulse)(uint32_t))
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121 | {
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122 | uint32_t counter = 640000;
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123 | uint8_t response = 0x00;
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124 |
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125 | noInterrupts();
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126 | sbus_uart_init();
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127 | sbus_timer_init();
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128 |
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129 | PinBasOutput(RECEIVE_PIN);
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130 | PinCasOutput(TRANSMIT_PIN);
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131 | PinCasOutput(PIN_4);
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132 |
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133 | disable_transmiting();
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134 | disable_receiving();
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135 |
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136 | UDR = 0xAA;
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137 | response = 0x00;
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138 | while(!(UCSRA & (1 << UDRE)));
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139 |
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140 | while ((counter > 1) && ( response != 0x55 ))
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141 | {
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142 | response = UDR;
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143 | while ( UCSRA & (1 << RXC) );
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144 | counter--;
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145 | }
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146 |
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147 | do_servo_pulls = (volatile void (*)(uint32_t))start_pulse;
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148 | start_receiving();
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149 |
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150 | if(response != 0x55 )
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151 | {
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152 | enable_receiving();
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153 | }
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154 | interrupts();
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155 |
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156 | }
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157 | /*
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158 | void SBUS2_uart_command_length(uint8_t length )
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159 | {
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160 | command_length = length;
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161 | }
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162 | */
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163 |
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164 | void sbus_uart_init()
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165 | {
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166 | // set clock divider
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167 | #undef BAUD
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168 | #define BAUD USART_BAUD
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169 |
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170 | #include <util/setbaud.h>
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171 |
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172 | UBRRH = UBRRH_VALUE;
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173 | UBRRL = UBRRL_VALUE;
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174 |
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175 | #if USE_2X
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176 | UCSRA |= (1 << U2X); // enable double speed operation
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177 | #else
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178 | UCSRA &= ~(1 << U2X); // disable double speed operation
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179 | #endif
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180 |
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181 | // set 8E2
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182 | UCSRC = (1 << UCSZ1) | (1 << UCSZ0);
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183 | UCSRB &= ~(1 << UCSZ2);
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184 |
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185 | UCSRC |= (1 << UPM1);
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186 | UCSRC |= (1 << USBS);
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187 |
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188 | // flush receive buffer
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189 | while ( UCSRA & (1 << RXC) ) UDR;
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190 |
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191 | UCSRB |= (1 << RXEN);
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192 | UCSRB |= (1 << RXCIE);
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193 | UCSRB |= (1 << TXEN);
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194 | UCSRB |= (1 << TXCIE);
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195 | }
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196 |
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197 | void sbus_timer_init()
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198 | {
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199 | //memset( (void*)transmit_data_per_slot, 0, sizeof(transmit_data_per_slot));
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200 | for(uint8_t i = 0; i < 32; i++)
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201 | {
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202 | transmit_data_per_slot_status[i] = EMPTY;
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203 | }
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204 |
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205 | TCCR2B = 0x00; //disable Timer2 while we set it up
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206 | TCNT2 = 0; //Reset Timer 0
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207 | TIFR2 = 0x02; //Timer2 INT Flag Reg: Clear Timer Overflow Flag
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208 | TIMSK2 = 0x03; //Timer2 INT Reg: Timer2 compare A
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209 | TCCR2A = 0x02; //Timer2 Control Reg A: CTC
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210 | }
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211 |
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212 | uint8_t SBUS_get_frame(uint8_t *frame)
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213 | {
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214 | if( frame_ready )
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215 | {
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216 | memcpy(frame, (void*)rxbuf, SBUS_FRAME_SIZE);
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217 | frame_ready = false;
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218 | return true;
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219 | }
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220 | else
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221 | {
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222 | return false;
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223 | }
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224 | }
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225 |
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226 | void start_receiving()
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227 | {
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228 | TCCR2B = 0x00; //disable Timer2 while we set it up
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229 | buffer_index = 0;
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230 | timer_ISR = (volatile void (*)())ISR_receive_timeout;
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231 | TCNT2 = 0; //Reset Timer 0
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232 | OCR2A = receive_timeout_timer;
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233 | }
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234 |
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235 | inline void disable_receiving()
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236 | {
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237 | PinBOutput( RECEIVE_PIN, TRANSMIT_RECEIVE_DISABLE);
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238 | }
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239 |
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240 | inline void enable_receiving()
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241 | {
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242 | PinCOutput( TRANSMIT_PIN, TRANSMIT_RECEIVE_DISABLE);
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243 | PinBOutput( RECEIVE_PIN, TRANSMIT_RECEIVE_ENABLE);
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244 | }
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245 |
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246 | inline void disable_transmiting()
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247 | {
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248 | PinCOutput( TRANSMIT_PIN, TRANSMIT_RECEIVE_DISABLE);
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249 | }
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250 |
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251 | inline void enable_transmiting()
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252 | {
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253 | PinBOutput( RECEIVE_PIN, TRANSMIT_RECEIVE_DISABLE);
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254 | PinCOutput( TRANSMIT_PIN, TRANSMIT_RECEIVE_ENABLE);
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255 | }
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256 |
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257 | ISR(TIMER2_COMPA_vect)
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258 | {
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259 | timer_ISR();
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260 | }
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261 |
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262 | inline void IncreaseTimer( int8_t frameNumber)
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263 | {
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264 | int8_t temp = (frameNumber - previousFrame) % NUMBER_OF_FRAMES;
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265 | if (temp <= 0 )
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266 | temp += NUMBER_OF_FRAMES;
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267 | if (temp > 1)
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268 | uart_lost_frame++;
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269 | frameCounter += temp;
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270 | previousFrame = frameNumber;
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271 | }
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272 |
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273 | ISR (USART_RX_vect)
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274 | {
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275 | uint8_t cdata = 0;
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276 |
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277 | frame_ready = false;
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278 | TCNT2 = 0; //Reset Timer 2 for new usart time of char
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279 | //enable Timer2 Control Reg B: for receive timeout this is done here because we can only start the timeout after first bye is received
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280 | TCCR2B = 0x03;
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281 | cdata = UDR;
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282 | rxbuf[buffer_index] = cdata;
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283 | buffer_index++;
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284 | if (buffer_index == SBUS_FRAME_SIZE)
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285 | {
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286 | frame_ready = true;
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287 | disable_receiving();
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288 | IncreaseTimer((cdata&0x30) >> 4);
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289 | start_transmit_sequencer(((cdata&0x30) >> 4)); // frame number needed to select correct telemetry slot
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290 |
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291 | if (do_servo_pulls != NULL )
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292 | {
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293 | do_servo_pulls(frameCounter * frameLength);
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294 | }
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295 | buffer_index = 0;
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296 | }
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297 | }
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298 |
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299 |
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300 | // receive timeout check for set packed length
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301 | void ISR_receive_timeout()
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302 | {
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303 | /* if ( buffer_index == command_length )
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304 | {
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305 | // -1 don't add crc in crc :-)
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306 | uint8_t crc = 0;
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307 | //crc = crc_cal( (uint8_t*)rxbuf, command_length -1);
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308 |
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309 | if ( (crc == rxbuf[command_length -1]) || true )
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310 | {
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311 | disable_receiving(); // this puts the module in setup mode
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312 | // setup command
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313 | memcpy(command, (void*)rxbuf, command_length);
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314 | command_received = true;
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315 | }
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316 | }
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317 | */
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318 | buffer_index = 0;
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319 | }
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320 |
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321 | //****************************************************************
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322 | //* TRANSMIT SEQUENCER
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323 | //****************************************************************
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324 |
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325 | void ISR_transmit()
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326 | {
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327 | static uint8_t sequence_count = 1; // first sequence step delay will be filled in when the transmit sequence is enabled
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328 | //Increments the interrupt counter
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329 | TCNT2 = 0; // reset at the beginning so that there is no delay for the next segment of the sequence
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330 |
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331 | interrupts();
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332 |
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333 | if (sequence_count < 2 )
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334 | {
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335 | // don't do anything this is delay to the transmission slots
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336 | OCR2A = transmit_sequence_timer[sequence_count];
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337 | }
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338 | else if (sequence_count < 10 ) // transmit slots
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339 | {
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340 | OCR2A = transmit_sequence_timer[sequence_count]; // first set next slot interrupt
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341 | sbus2_send_slot((sequence_count-2) + (gl_current_frame * NUMBER_OF_SLOT_IN_FRAME) );
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342 | }
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343 | else if (sequence_count < 11 )
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344 | {
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345 | OCR2A = transmit_sequence_timer[sequence_count];
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346 |
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347 | }
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348 | else if (sequence_count < 14 )
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349 | {
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350 | // delay to enabling receive again
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351 | OCR2A = transmit_sequence_timer[sequence_count];
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352 | }
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353 | else if (sequence_count < 15 )
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354 | {
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355 | // delay to enabling receive again
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356 | OCR2A = transmit_sequence_timer[sequence_count];
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357 | frame_ready = false; // this will give ms to collect the servo data
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358 | }
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359 | else
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360 | {
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361 | // reset transmit sequencer
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362 | TCCR2B = 0x00; //Disbale Timer2 while we set it up
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363 | sequence_count = 0; // first sequence step delay will be filled in when the transmit sequence is enabled
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364 |
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365 | enable_receiving();
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366 | start_receiving();
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367 | }
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368 | sequence_count++;
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369 |
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370 | TIFR2 = 0x00; //Timer2 INT Flag Reg: Clear Timer Overflow Flag
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371 | };
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372 |
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373 | ISR(TIMER2_OVF_vect)
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374 | {
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375 | // for debugging should not occur
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376 | overflow_counter++;
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377 | };
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378 |
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379 |
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380 | void start_transmit_sequencer(uint8_t frame_number)
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381 | {
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382 | //set transmit ISR
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383 | timer_ISR = (volatile void (*)())ISR_transmit;
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384 |
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385 | OCR2A = transmit_sequence_timer[0]; //set first delay value
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386 | TCCR2B = 0x03; //enable Timer2 Control Reg B: Timer Prescaler set to 128
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387 |
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388 | gl_current_frame = frame_number;
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389 | }
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390 |
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391 |
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392 | //****************************************************************
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393 | //* TRANSMIT usart send
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394 | //****************************************************************
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395 | void sbus2_send_slot(uint8_t slot)
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396 | {
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397 | // if data available in slot then send it
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398 | if ( transmit_data_per_slot_status[slot] == AVAILABLE )
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399 | {
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400 |
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401 | transmit_data_per_slot_status[slot] = TRANSMITTING;
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402 | enable_transmiting();
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403 | //sending_slot = &transmit_data_per_slot[slot];
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404 | gl_slot = slot;
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405 | //send first byte
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406 | UDR = transmit_data_per_slot_data[gl_slot][0]; // the reset will be done by TX ISR
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407 | tx_data_counter = 1;
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408 | }
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409 | }
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410 |
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411 | ISR (USART_TX_vect)
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412 | {
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413 | interrupts();
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414 | if (transmit_data_per_slot_status[gl_slot] != EMPTY)
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415 | {
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416 | if ( tx_data_counter < SLOT_DATA_LENGTH )
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417 | {
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418 | UDR = transmit_data_per_slot_data[gl_slot][tx_data_counter];
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419 | tx_data_counter++;
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420 | }
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421 | else
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422 | {
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423 | // disable transmitter line and set data status to empty so that it can be written again
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424 | disable_transmiting();
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425 | transmit_data_per_slot_status[gl_slot] = EMPTY;
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426 | }
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427 | }
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428 | }
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429 |
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430 | void SBUS2_transmit_telemetry_data( uint8_t slot, uint8_t data[SLOT_DATA_LENGTH] )
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431 | {
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432 | uint8_t swapped_slot = 0;
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433 | if ( transmit_data_per_slot_status[slot] != TRANSMITTING )
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434 | {
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435 | //swap slot ID
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436 | swapped_slot = swaps_slot_bits[slot % 8] << 5;
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437 | memcpy( (void*)transmit_data_per_slot_data[slot], data, SLOT_DATA_LENGTH);
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438 | transmit_data_per_slot_data[slot][0] &= 0x1F; // reset frame slot ID
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439 | transmit_data_per_slot_data[slot][0] |= swapped_slot;
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440 |
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441 | transmit_data_per_slot_status[slot] = AVAILABLE;
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442 | }
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443 | }
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444 |
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445 | bool SBUS2_get_all_servo_data( uint16_t channels[16] )
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446 | {
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447 | if ( frame_ready )
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448 | {
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449 | uint8_t byte_in_sbus = 1;
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450 | uint16_t bit_in_sbus = 0;
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451 | uint8_t ch = 0;
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452 | uint16_t bit_in_channel = 0;
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453 | //uint16_t temp;
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454 | uint8_t channel_data[UART_RXBUFSIZE];
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455 | //noInterrupts();
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456 | memcpy(channel_data, (void*)rxbuf, 24);
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457 | //interrupts();
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458 |
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459 | for (uint8_t i=0; i<16; i++)
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460 | channels[i] = 0;
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461 |
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462 | // process actual sbus data
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463 | for (uint8_t i=0; i<176; i++)
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464 | {
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465 | //temp = 1<<bit_in_sbus;
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466 | if (channel_data[byte_in_sbus] & (1<<bit_in_sbus))
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467 | {
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468 | //temp = (1<<bit_in_channel);
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469 | channels[ch] |= (1<<bit_in_channel);
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470 | }
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471 | bit_in_sbus++;
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472 | bit_in_channel++;
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473 |
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474 | if (bit_in_sbus == 8)
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475 | {
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476 | bit_in_sbus =0;
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477 | byte_in_sbus++;
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478 | }
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479 | if (bit_in_channel == 11)
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480 | {
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481 | bit_in_channel =0;
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482 | ch++;
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483 | }
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484 | }
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485 | // DigiChannel 1
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486 | if (channel_data[23] & (1<<0))
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487 | {
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488 | channels[16] = 1;
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489 | }
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490 | else
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491 | {
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492 | channels[16] = 0;
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493 | }
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494 | // DigiChannel 2
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495 | if (channel_data[23] & (1<<1))
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496 | {
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497 | channels[17] = 1;
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498 | }
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499 | else
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500 | {
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501 | channels[17] = 0;
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502 | }
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503 |
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504 | return true;
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505 | }
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506 | else
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507 | {
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508 | return false;
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509 | }
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510 | }
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511 |
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512 |
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513 | void SBUS2_get_status( uint16_t *uart_dropped_frame, bool *transmision_dropt_frame, bool *failsave )
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514 | {
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515 | if (frameCounter < 60)
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516 | {
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517 | uart_lost_frame = 0;
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518 | }
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519 | *uart_dropped_frame = uart_lost_frame;
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520 | *transmision_dropt_frame = rxbuf[23] & 0x20 ? true : false;
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521 | *failsave = rxbuf[23] & 0x10 ? true : false;
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522 | }
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523 |
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524 | /*
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525 | bool SBUS2_get_command( uint8_t *p_command )
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526 | {
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527 | if (command_received)
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528 | {
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529 | memcpy(p_command, command, command_length);
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530 | command_received = false;
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531 |
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532 | return true;
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533 | }
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534 | return false;
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535 | }
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536 |
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537 |
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538 | void SBUS2_send_command( uint8_t *p_command )
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539 | {
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540 | int index = 0;
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541 |
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542 | for( index = 0; index < command_length; index++)
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543 | {
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544 | while( !(UCSRA & (1<<UDRE))){}
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545 | UDR = p_command[index];
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546 | }
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547 | }
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548 | */
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549 |
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550 | int16_t SBUS2_get_servo_data( uint8_t channel )
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551 | {
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552 | uint8_t byte_in_sbus = 1;
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553 | uint16_t bit_in_sbus = 0;
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554 | uint8_t ch = 0;
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555 | uint16_t bit_in_channel = 0;
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556 | uint8_t channel_data[UART_RXBUFSIZE];
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557 |
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558 | uint16_t servo = 0;
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559 | uint8_t start_bit = 0;
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560 |
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561 | //noInterrupts();
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562 | memcpy(channel_data, (void*)rxbuf, 24);
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563 | //interrupts();
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564 |
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565 | if ( frame_ready )
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566 | {
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567 | start_bit = channel * SBUS_CHANNEL_SIZE ;
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568 | bit_in_sbus = start_bit % 8;
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569 | byte_in_sbus = (start_bit / 8) + 1;
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570 |
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571 | // process actual sbus data
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572 | for (uint8_t i=start_bit; i<(start_bit+11); i++)
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573 | {
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574 | if (channel_data[byte_in_sbus] & (1<<bit_in_sbus))
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575 | {
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576 | servo |= (1<<bit_in_channel);
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577 | }
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578 | bit_in_sbus++;
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579 | bit_in_channel++;
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580 |
|
581 | if (bit_in_sbus == 8)
|
582 | {
|
583 | bit_in_sbus =0;
|
584 | byte_in_sbus++;
|
585 | }
|
586 | if (bit_in_channel == 11)
|
587 | {
|
588 | bit_in_channel =0;
|
589 | ch++;
|
590 | }
|
591 | }
|
592 | return (int16_t)servo;
|
593 | }
|
594 | else
|
595 | {
|
596 | return -1;
|
597 | }
|
598 | }
|