Im trying to generate PWM signals. Why its not showing any contents' in ILA core? Differential clock(sysclk_p and n) is 100Mhz and clk_out1 is 100mhz. Contraint file ## Clock Signal set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVDS} [get_ports sysclk_n] set_property -dict {PACKAGE_PIN AD12 IOSTANDARD LVDS} [get_ports sysclk_p] ## Buttons set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports reset_n] set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports decrease_duty] set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports increase_duty] set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports cpu_resetn] ## LEDs set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports PWM_OUT] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[11]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[25]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[21]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[12]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[3]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[19]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[17]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[9]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[10]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[24]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[26]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[15]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[4]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[1]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[20]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[0]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[23]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[16]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[8]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[22]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[13]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[14]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[5]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[6]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[27]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[2]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[7]}] set_property MARK_DEBUG true [get_nets {counter_debounce_reg[18]}] set_property MARK_DEBUG true [get_nets {counter_PWM_reg__0[7]}] set_property MARK_DEBUG true [get_nets {counter_PWM_reg__0[4]}] set_property MARK_DEBUG true [get_nets {counter_PWM_reg__0[3]}] set_property MARK_DEBUG true [get_nets {counter_PWM_reg__0[1]}] set_property MARK_DEBUG true [get_nets {counter_PWM_reg__0[0]}] set_property MARK_DEBUG true [get_nets {counter_PWM_reg__0[5]}] set_property MARK_DEBUG true [get_nets {counter_PWM_reg__0[2]}] set_property MARK_DEBUG true [get_nets {counter_PWM_reg__0[6]}] set_property MARK_DEBUG true [get_nets {DUTY_CYCLE[6]}] set_property MARK_DEBUG true [get_nets {DUTY_CYCLE[7]}] set_property MARK_DEBUG true [get_nets {DUTY_CYCLE[5]}] set_property MARK_DEBUG true [get_nets {DUTY_CYCLE[2]}] set_property MARK_DEBUG true [get_nets {DUTY_CYCLE[1]}] set_property MARK_DEBUG true [get_nets {DUTY_CYCLE[0]}] set_property MARK_DEBUG true [get_nets {DUTY_CYCLE[4]}] set_property MARK_DEBUG true [get_nets {DUTY_CYCLE[3]}] set_property MARK_DEBUG true [get_nets decrease_duty_IBUF] set_property MARK_DEBUG true [get_nets increase_duty_IBUF] set_property MARK_DEBUG true [get_nets PWM_OUT_OBUF] create_debug_core u_ila_0 ila set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0] set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] set_property port_width 1 [get_debug_ports u_ila_0/clk] connect_debug_port u_ila_0/clk [get_nets [list clk_gen/inst/clk_out]] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0] set_property port_width 28 [get_debug_ports u_ila_0/probe0] connect_debug_port u_ila_0/probe0 [get_nets [list {counter_debounce_reg[0]} {counter_debounce_reg[1]} {counter_debounce_reg[2]} {counter_debounce_reg[3]} {counter_debounce_reg[4]} {counter_debounce_reg[5]} {counter_debounce_reg[6]} {counter_debounce_reg[7]} {counter_debounce_reg[8]} {counter_debounce_reg[9]} {counter_debounce_reg[10]} {counter_debounce_reg[11]} {counter_debounce_reg[12]} {counter_debounce_reg[13]} {counter_debounce_reg[14]} {counter_debounce_reg[15]} {counter_debounce_reg[16]} {counter_debounce_reg[17]} {counter_debounce_reg[18]} {counter_debounce_reg[19]} {counter_debounce_reg[20]} {counter_debounce_reg[21]} {counter_debounce_reg[22]} {counter_debounce_reg[23]} {counter_debounce_reg[24]} {counter_debounce_reg[25]} {counter_debounce_reg[26]} {counter_debounce_reg[27]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1] set_property port_width 8 [get_debug_ports u_ila_0/probe1] connect_debug_port u_ila_0/probe1 [get_nets [list {DUTY_CYCLE[0]} {DUTY_CYCLE[1]} {DUTY_CYCLE[2]} {DUTY_CYCLE[3]} {DUTY_CYCLE[4]} {DUTY_CYCLE[5]} {DUTY_CYCLE[6]} {DUTY_CYCLE[7]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2] set_property port_width 8 [get_debug_ports u_ila_0/probe2] connect_debug_port u_ila_0/probe2 [get_nets [list {counter_PWM_reg__0[0]} {counter_PWM_reg__0[1]} {counter_PWM_reg__0[2]} {counter_PWM_reg__0[3]} {counter_PWM_reg__0[4]} {counter_PWM_reg__0[5]} {counter_PWM_reg__0[6]} {counter_PWM_reg__0[7]}]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3] set_property port_width 1 [get_debug_ports u_ila_0/probe3] connect_debug_port u_ila_0/probe3 [get_nets [list decrease_duty_IBUF]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4] set_property port_width 1 [get_debug_ports u_ila_0/probe4] connect_debug_port u_ila_0/probe4 [get_nets [list increase_duty_IBUF]] create_debug_port u_ila_0 probe set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5] set_property port_width 1 [get_debug_ports u_ila_0/probe5] connect_debug_port u_ila_0/probe5 [get_nets [list PWM_OUT_OBUF]] set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub] set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub] connect_debug_port dbg_hub/clk [get_nets clk]
Adira N. schrieb: > Im trying to generate PWM signals. Why its not showing any contents' in > ILA core? Maybe because it has been optimized to zero, becaus the ila has no (visible) output port. See map report file, try atributes KEEP and/or NOPRUNE, depending on the synhtesis tool you're playing with.
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