1 | // PIC18F25K50 Configuration Bit Settings
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2 |
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3 | // 'C' source line config statements
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4 |
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5 | // CONFIG1L
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6 | #pragma config PLLSEL = PLL3X // PLL Selection (3x clock multiplier)
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7 | #pragma config CFGPLLEN = ON // PLL Enable Configuration bit (PLL Enabled)
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8 | #pragma config CPUDIV = NOCLKDIV// CPU System Clock Postscaler (CPU uses system clock (no divide))
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9 | #pragma config LS48MHZ = SYS48X8// Low Speed USB mode with 48 MHz system clock (System clock at 48 MHz, USB clock divider is set to 8)
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10 |
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11 | // CONFIG1H
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12 | #pragma config FOSC = HSH // Oscillator Selection (HS oscillator, high power 16MHz to 25MHz)
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13 | #pragma config PCLKEN = OFF // Primary Oscillator Shutdown (Primary oscillator shutdown firmware controlled)
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14 | #pragma config FCMEN = OFF // Fail-Safe Clock Monitor (Fail-Safe Clock Monitor disabled)
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15 | #pragma config IESO = OFF // Internal/External Oscillator Switchover (Oscillator Switchover mode disabled)
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16 |
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17 | // CONFIG2L
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18 | #pragma config nPWRTEN = ON // Power-up Timer Enable (Power up timer enabled)
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19 | #pragma config BOREN = ON // Brown-out Reset Enable (BOR controlled by firmware (SBOREN is enabled))
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20 | #pragma config BORV = 285 // Brown-out Reset Voltage (BOR set to 2.85V nominal)
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21 | #pragma config nLPBOR = ON // Low-Power Brown-out Reset (Low-Power Brown-out Reset enabled)
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22 |
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23 | // CONFIG2H
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24 | #pragma config WDTEN = SWON // Watchdog Timer Enable bits (WDT controlled by firmware (SWDTEN enabled))
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25 | #pragma config WDTPS = 256 // Watchdog Timer Postscaler (1:256)
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26 |
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27 | // CONFIG3H
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28 | #pragma config CCP2MX = RC1 // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
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29 | #pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<5:0> pins are configured as analog input channels on Reset)
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30 | #pragma config T3CMX = RC0 // Timer3 Clock Input MUX bit (T3CKI function is on RC0)
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31 | #pragma config SDOMX = RB3 // SDO Output MUX bit (SDO function is on RB3)
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32 | #pragma config MCLRE = ON // Master Clear Reset Pin Enable (MCLR pin enabled; RE3 input disabled)
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33 |
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34 | // CONFIG4L
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35 | #pragma config STVREN = ON // Stack Full/Underflow Reset (Stack full/underflow will cause Reset)
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36 | #pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled if MCLRE is also 1)
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37 | #pragma config ICPRT = OFF // Dedicated In-Circuit Debug/Programming Port Enable (ICPORT disabled)
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38 | #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled)
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39 |
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40 | // CONFIG5L
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41 | #pragma config CP0 = ON // Block 0 Code Protect (Block 0 is code-protected)
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42 | #pragma config CP1 = OFF // Block 1 Code Protect (Block 1 is not code-protected)
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43 | #pragma config CP2 = OFF // Block 2 Code Protect (Block 2 is not code-protected)
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44 | #pragma config CP3 = OFF // Block 3 Code Protect (Block 3 is not code-protected)
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45 |
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46 | // CONFIG5H
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47 | #pragma config CPB = OFF // Boot Block Code Protect (Boot block is not code-protected)
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48 | #pragma config CPD = OFF // Data EEPROM Code Protect (Data EEPROM is not code-protected)
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49 |
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50 | // CONFIG6L
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51 | #pragma config WRT0 = ON // Block 0 Write Protect (Block 0 (0800-1FFFh) is write-protected)
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52 | #pragma config WRT1 = OFF // Block 1 Write Protect (Block 1 (2000-3FFFh) is not write-protected)
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53 | #pragma config WRT2 = OFF // Block 2 Write Protect (Block 2 (04000-5FFFh) is not write-protected)
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54 | #pragma config WRT3 = OFF // Block 3 Write Protect (Block 3 (06000-7FFFh) is not write-protected)
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55 |
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56 | // CONFIG6H
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57 | #pragma config WRTC = ON // Configuration Registers Write Protect (Configuration registers (300000-3000FFh) are write-protected)
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58 | #pragma config WRTB = ON // Boot Block Write Protect (Boot block (0000-7FFh) is write-protected)
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59 | #pragma config WRTD = OFF // Data EEPROM Write Protect (Data EEPROM is not write-protected)
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60 |
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61 | // CONFIG7L
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62 | #pragma config EBTR0 = ON // Block 0 Table Read Protect (Block 0 is protected from table reads executed in other blocks)
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63 | #pragma config EBTR1 = OFF // Block 1 Table Read Protect (Block 1 is not protected from table reads executed in other blocks)
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64 | #pragma config EBTR2 = OFF // Block 2 Table Read Protect (Block 2 is not protected from table reads executed in other blocks)
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65 | #pragma config EBTR3 = OFF // Block 3 Table Read Protect (Block 3 is not protected from table reads executed in other blocks)
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66 |
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67 | // CONFIG7H
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68 | #pragma config EBTRB = OFF // Boot Block Table Read Protect (Boot block is not protected from table reads executed in other blocks)
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69 |
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70 | // #pragma config statements should precede project file includes.
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71 | // Use project enums instead of #define for ON and OFF.
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72 |
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73 | #include <xc.h>
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