Hallo Leute
Ich arbeite seit einer Woche mit VHDL
Ich hab einen Zähler implementiert der auch funktioniert.
Der Zählerstand wird dann in meinen FIFO geladen (also es wird im FIFO
geschrieben) Die Module habe ich über Signale miteinander verbunden.
Man erkennt auch, dass der Eingang meines Speichers (Din) den selben
Zählerstand des Ausgangs meines Schreibmodul hat. Was ich jetzt aber
nicht verstehe ist, dass mein Lesemodul diesen Zählerstand nicht lesen
kann...
Ich würde mich freuen Wenn mein Speicher am Ausgang überhaupt einen
Zählerstand ungleich 0 ausgibt. Habt ihr eventuell eine Ahnung woran es
liegen kann? Der Schreibvorgang funktioniert ja
****************Code Schreibmodul***********************
1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.NUMERIC_STD.ALL
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4 |
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5 | entity write_m is
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6 |
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7 | port(
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8 | clk : in std_logic;
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9 | rst : in std_logic;
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10 | enable_w : in std_logic;
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11 | d_out : out std_logic_vector(17 downto 0);
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12 | w_out : out std_logic;
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13 | full : in std_logic
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14 | );
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15 |
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16 | end write_m;
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17 |
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18 | architecture Behavioral of write_m is
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19 |
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20 | signal d_out_1 : std_logic_vector(17 downto 0);
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21 |
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22 | begin
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23 |
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24 | process(rst,clk)
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25 | begin
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26 | if(rst = '1') then
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27 | d_out_1 <= (others => '0');
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28 | w_out <= '0';
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29 | elsif (clk = '1') and clk'event then
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30 | if (enable_w = '1' and full = '0') then
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31 | w_out <= '1';
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32 | d_out_1 <= std_logic_vector(unsigned(d_out_1)+1);
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33 | else
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34 | d_out_1 <= std_logic_vector(unsigned(d_out_1));
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35 | w_out <= '0';
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36 | end if;
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37 | end if;
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38 | end process;
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39 |
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40 | d_out <= d_out_1;
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41 | end Behavioral;
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**************Code Lesemodul****************
1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.NUMERIC_STD.ALL
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4 |
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5 | entity read_m is
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6 | port(
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7 | clk : in std_logic;
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8 | rst : in std_logic;
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9 | d_in_r : in std_logic_vector(17 downto 0);
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10 | empty : in std_logic;
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11 | enable_r : in std_logic;
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12 | d_out : out std_logic_vector(17 downto 0);
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13 | r_out : out std_logic
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14 | );
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15 |
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16 |
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17 | end read_m;
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18 |
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19 | architecture Behavioral of read_m is
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20 | signal d_out_1 : std_logic_vector(17 downto 0);
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21 |
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22 | begin
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23 | process(rst,clk)
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24 | begin
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25 | if(rst = '0') then
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26 | d_out_1 <= (others => '0');
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27 | r_out <= '0';
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28 | if (clk = '1') and clk'event then
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29 | if (enable_r = '1' and empty = '0') then
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30 | r_out <= '1';
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31 | d_out_1 <= std_logic_vector(unsigned(d_in_r));
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32 | end if;
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33 | end if;
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34 | end if;
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35 | end process;
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36 |
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37 | d_out <= d_out_1;
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38 |
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39 | end Behavioral;
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****Speicher(FIFO mit IP Core generiert)************
***********TOPMODUL***************************
1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.NUMERIC_STD.ALL
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4 |
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5 | entity TOP is
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6 | port (
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7 | clk : in std_logic;
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8 | rst : in std_logic;
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9 | enable_w : in std_logic;
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10 | enable_r : in std_logic;
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11 | d_out : out std_logic_vector(17 downto 0)
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12 | );
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13 | end TOP;
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14 |
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15 | architecture Behavioral of TOP is
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16 |
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17 |
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18 |
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19 | component write_m
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20 |
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21 | port(
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22 | clk : in std_logic;
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23 | rst : in std_logic;
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24 | enable_w : in std_logic;
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25 | d_out : out std_logic_vector(17 downto 0);
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26 | w_out : out std_logic;
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27 | full : in std_logic
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28 | END COMPONENT;
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29 |
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30 |
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31 |
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32 |
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33 | COMPONENT fifo_neu
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34 | PORT (
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35 | clk : IN STD_LOGIC;
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36 | rst : IN STD_LOGIC;
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37 | din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
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38 | wr_en : IN STD_LOGIC;
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39 | rd_en : IN STD_LOGIC;
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40 | dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
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41 | full : OUT STD_LOGIC;
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42 | empty : OUT STD_LOGIC
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43 | );
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44 | END COMPONENT;
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45 |
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46 |
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47 | component read_m
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48 | port(
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49 | clk : in std_logic;
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50 | rst : in std_logic;
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51 | d_in_r : in std_logic_vector(17 downto 0);
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52 | empty : in std_logic;
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53 | enable_r : in std_logic;
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54 | d_out : out std_logic_vector(17 downto 0);
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55 | r_out : out std_logic
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56 | );
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57 | end component;
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58 |
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59 |
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60 |
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61 |
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62 |
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63 |
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64 |
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65 | signal fifo_out : std_logic_vector(17 downto 0);
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66 | signal fifo_in : std_logic_vector(17 downto 0);
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67 | signal fifo_wr : std_logic;
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68 | signal fifo_full : std_logic;
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69 | signal fifo_empty : std_logic;
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70 | signal fifo_rd : std_logic;
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71 |
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72 | begin
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73 |
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74 |
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75 | your_instance_name : fifo_neu
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76 | PORT MAP (
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77 | clk => clk,
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78 | rst => rst,
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79 | din => fifo_in,
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80 | wr_en => fifo_wr,
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81 | rd_en => fifo_rd,
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82 | dout => fifo_out,
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83 | full => fifo_full,
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84 | empty => fifo_empty
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85 | );
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86 |
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87 | write_i : write_m
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88 | Port Map(
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89 | clk => clk,
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90 | rst => rst,
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91 | enable_w => enable_w,
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92 | d_out => fifo_in,
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93 | w_out => fifo_wr,
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94 | full => fifo_full
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95 | );
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96 |
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97 |
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98 | read_i : read_m
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99 | port map(
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100 |
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101 | clk => clk,
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102 | rst => rst,
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103 | enable_r => enable_r,
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104 | d_in_r => fifo_out,
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105 | empty => fifo_empty,
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106 | d_out => d_out,
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107 | r_out => fifo_rd
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108 | );
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109 |
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110 |
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111 | end Behavioral;
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***********Testbench von TOP ************
1 | LIBRARY ieee;
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2 | USE ieee.std_logic_1164.ALL;
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3 |
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4 | -- Uncomment the following library declaration if using
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5 | -- arithmetic functions with Signed or Unsigned values
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6 | --USE ieee.numeric_std.ALL;
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7 |
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8 | ENTITY TOP_2tb IS
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9 | END TOP_2tb;
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10 |
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11 | ARCHITECTURE behavior OF TOP_2tb IS
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12 |
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13 | -- Component Declaration for the Unit Under Test (UUT)
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14 |
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15 | COMPONENT TOP
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16 | PORT(
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17 | clk : IN std_logic;
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18 | rst : IN std_logic;
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19 | enable_w : IN std_logic;
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20 | enable_r : IN std_logic;
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21 | d_out : OUT std_logic_vector(17 downto 0)
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22 | );
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23 | END COMPONENT;
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24 |
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25 |
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26 | --Inputs
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27 | signal clk : std_logic := '0';
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28 | signal rst : std_logic := '0';
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29 | signal enable_w : std_logic := '0';
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30 | signal enable_r : std_logic := '0';
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31 |
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32 | --Outputs
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33 | signal d_out : std_logic_vector(17 downto 0);
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34 |
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35 | -- Clock period definitions
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36 | constant clk_period : time := 10 ns;
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37 |
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38 | BEGIN
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39 |
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40 | -- Instantiate the Unit Under Test (UUT)
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41 | uut: TOP PORT MAP (
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42 | clk => clk,
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43 | rst => rst,
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44 | enable_w => enable_w,
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45 | enable_r => enable_r,
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46 | d_out => d_out
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47 | );
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48 |
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49 | -- Clock process definitions
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50 | clk_process :process
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51 | begin
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52 | clk <= '0';
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53 | wait for clk_period/2;
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54 | clk <= '1';
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55 | wait for clk_period/2;
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56 | end process;
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57 |
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58 |
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59 | -- Stimulus process
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60 | stim_proc: process
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61 | begin
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62 | --Reset
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63 | rst <= '1';
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64 | wait for 20 ns;
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65 | rst <= '0';
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66 |
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67 | --Write
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68 | enable_W <= '1';
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69 | wait for 350 ns;
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70 |
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71 | --Write and Read
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72 | enable_R <= '1';
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73 | wait for 100 ns;
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74 |
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75 | --Read
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76 | enable_W <= '0';
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77 | wait for 350 ns;
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78 |
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79 | --No operation
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80 | enable_R <= '0';
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81 |
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82 | wait for clk_period*10;
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83 | wait;
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84 | end process;
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85 |
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86 | END;
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