Moin,
ich möchte ein CLK-Enable umsetzen. Dazu möchte ich den Systemtakt von
100MHz eines FPGAs auf 60Hz runtertakten. Der Teile wäre somit
100MHz/60Hz=1.666.667.
Ich habe das jetzt folgendermaßen umgesetzt:
1 | --library UNISIM;
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2 | --use UNISIM.VComponents.all;
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3 |
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4 | entity PWM_MODULE_CLK_EN is
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5 | -- Port ( );
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6 | generic(P: integer := 1666667);
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7 | port(
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8 | CLK_100MHZ_PIN: in std_logic;
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9 | ARESETN_PIN: in std_logic;
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10 | CLK_EN_OUT: out std_logic
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11 | );
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12 | end PWM_MODULE_CLK_EN;
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13 |
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14 | architecture Behavioral of PWM_MODULE_CLK_EN is
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15 | -- counter state reg
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16 | signal COUNTER: integer range 0 to 1666667;
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17 | signal Q, Q_NEXT: unsigned(P-1 downto 0);
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18 | begin
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19 | -- counter
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20 | PWM_MODULE_CLK_EN_REG: process(CLK_100MHZ_PIN)
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21 | begin
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22 | if CLK_100MHZ_PIN = '1' and CLK_100MHZ_PIN'event then
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23 | if(ARESETN_PIN = '0') then
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24 | COUNTER <= 0 after 2 ns;
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25 | Q <= (others => '0') after 2 ns;
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26 | else
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27 | Q <= Q_NEXT after 2 ns;
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28 | end if;
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29 | end if;
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30 | end process;
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31 |
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32 | -- increment and create enable pulse every p cycle
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33 | PWM_MODULE_CLK_EN_CMB: process(Q)
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34 | begin
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35 | CLK_EN_OUT <= '0' after 2 ns;
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36 | -- output logic
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37 | if Q = P-1 then
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38 | CLK_EN_OUT <= '1' after 2 ns;
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39 | end if;
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40 | --next state logic
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41 | Q_NEXT <= Q + 1 after 2 ns;
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42 | end process;
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43 |
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44 | end Behavioral;
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Ich hätte den Pre-Scaler aber lieber als Potenz angegeben. Also eher so:
1 | --library UNISIM;
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2 | --use UNISIM.VComponents.all;
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3 |
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4 | entity PWM_MODULE_CLK_EN is
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5 | -- Port ( );
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6 | generic(P: integer := 21);
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7 | port(
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8 | CLK_100MHZ_PIN: in std_logic;
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9 | ARESETN_PIN: in std_logic;
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10 | CLK_EN_OUT: out std_logic
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11 | );
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12 | end PWM_MODULE_CLK_EN;
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13 |
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14 | architecture Behavioral of PWM_MODULE_CLK_EN is
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15 | -- counter state reg
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16 | signal Q, Q_NEXT: unsigned(P-1 downto 0);
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17 | begin
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18 | -- counter
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19 | PWM_MODULE_CLK_EN_REG: process(CLK_100MHZ_PIN)
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20 | begin
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21 | if CLK_100MHZ_PIN = '1' and CLK_100MHZ_PIN'event then
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22 | if(ARESETN_PIN = '0') then
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23 | Q <= (others => '0') after 2 ns;
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24 | else
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25 | Q <= Q_NEXT after 2 ns;
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26 | end if;
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27 | end if;
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28 | end process;
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29 |
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30 | -- increment and create enable pulse every p cycle
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31 | PWM_MODULE_CLK_EN_CMB: process(Q)
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32 | begin
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33 | CLK_EN_OUT <= '0' after 2 ns;
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34 | -- output logic
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35 | if Q = 2**P-1 then
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36 | CLK_EN_OUT <= '1' after 2 ns;
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37 | end if;
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38 | --next state logic
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39 | Q_NEXT <= Q + 1 after 2 ns;
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40 | end process;
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41 |
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42 | end Behavioral;
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P wäre dann allerdings P=log2(1666667)=20,669. Kann mir da einer auf die
Sprünge helfen, wie das trotz einer Fließkommazahl umsetzbar ist?